公开(公告)号：US20060199318A1

公开(公告)日：2006-09-07

申请号：US11416132

申请日：2006-05-03

申请人： Takayoshi Minami ,  Yuji Setta

发明人： Takayoshi Minami ,  Yuji Setta

IPC分类号： H01L21/84

CPC分类号： H01L21/76895 ,  H01L21/823871 ,  H01L27/11 ,  H01L27/1104

摘要： The semiconductor device comprises a gate interconnection 24a including a gate electrode formed over a semiconductor substrate 14 with a gate insulation film 22 formed therebetween; a first source/drain diffused layer 28 formed near the end of the gate interconnection 24a; a second source/drain diffused layer 34 formed remote from the gate interconnection 24a and the first source/drain diffused layer 28; and an insulation film 40 formed over the gate interconnection 24a, the first source/drain diffused layer 28 and the second source/drain diffused layer 34, and having a groove-shaped opening 42a formed in, which integrally exposes the gate interconnection 24a, one of the first source/drain diffused layer 28, and one of the second source/drain diffused layer 34; and a contact layer 48a buried in the groove-shaped opening 42a. The groove-shaped openings 42a for the contact layers 48a to be buried in can be formed without failure. Accordingly, it is possible to provide a semiconductor device which can realize the micronization without reliability decrease and fabrication yield decrease.

公开(公告)号：US20050040468A1

公开(公告)日：2005-02-24

申请号：US10788379

申请日：2004-03-01

申请人： Takayoshi Minami ,  Yuji Setta

发明人： Takayoshi Minami ,  Yuji Setta

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/792

CPC分类号： H01L21/76895 ,  H01L21/823871 ,  H01L27/11 ,  H01L27/1104

摘要： The semiconductor device comprises a gate interconnection 24a including a gate electrode formed over a semiconductor substrate 14 with a gate insulation film 22 formed therebetween; a first source/drain diffused layer 28 formed near the end of the gate interconnection 24a; a second source/drain diffused layer 34 formed remote from the gate interconnection 24a and the first source/drain diffused layer 28; and an insulation film 40 formed over the gate interconnection 24a, the first source/drain diffused layer 28 and the second source/drain diffused layer 34, and having a groove-shaped opening 42a formed in, which integrally exposes the gate interconnection 24a, one of the first source/drain diffused layer 28, and one of the second source/drain diffused layer 34; and a contact layer 48a buried in the groove-shaped opening 42a. The groove-shaped openings 42a for the contact layers 48a to be buried in can be formed without failure. Accordingly, it is possible to provide a semiconductor device which can realize the micronization without reliability decrease and fabrication yield decrease.

摘要翻译： 半导体器件包括栅极互连24a，其包括在半导体衬底14上形成的栅电极，其间形成有栅极绝缘膜22; 在门互连24a的端部附近形成的第一源极/漏极扩散层28; 远离栅极互连24a和第一源极/漏极扩散层28形成的第二源极/漏极扩散层34; 以及形成在栅极布线24a，第一源极/漏极扩散层28和第二源极/漏极扩散层34上的绝缘膜40，并且具有形成在其中的沟槽形开口42a，其一体地暴露栅极互连24a，一个 第一源极/漏极扩散层28和第二源极/漏极扩散层34之一; 以及埋设在槽形开口42a中的接触层48a。 可以形成用于埋入的接触层48a的槽形开口42a而不会发生故障。 因此，可以提供一种能够实现微粉化而不降低可靠性并降低制造成品率的半导体器件。

公开(公告)号：US07138312B2

公开(公告)日：2006-11-21

申请号：US11416132

申请日：2006-05-03

申请人： Takayoshi Minami ,  Yuji Setta

发明人： Takayoshi Minami ,  Yuji Setta

IPC分类号： H01L21/8238

CPC分类号： H01L21/76895 ,  H01L21/823871 ,  H01L27/11 ,  H01L27/1104

摘要： The semiconductor device comprises a gate interconnection 24a including a gate electrode formed over a semiconductor substrate 14 with a gate insulation film 22 formed therebetween; a first source/drain diffused layer 28 formed near the end of the gate interconnection 24a; a second source/drain diffused layer 34 formed remote from the gate interconnection 24a and the first source/drain diffused layer 28; and an insulation film 40 formed over the gate interconnection 24a, the first source/drain diffused layer 28 and the second source/drain diffused layer 34, and having a groove-shaped opening 42a formed in, which integrally exposes the gate interconnection 24a, one of the first source/drain diffused layer 28, and one of the second source/drain diffused layer 34; and a contact layer 48a buried in the groove-shaped opening 42a. The groove-shaped openings 42a for the contact layers 48a to be buried in can be formed without failure. Accordingly, it is possible to provide a semiconductor device which can realize the micronization without reliability decrease and fabrication yield decrease.

公开(公告)号：US07064395B2

公开(公告)日：2006-06-20

申请号：US10788379

申请日：2004-03-01

申请人： Takayoshi Minami ,  Yuji Setta

发明人： Takayoshi Minami ,  Yuji Setta

IPC分类号： H01L29/76 ,  H01L29/54 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76895 ,  H01L21/823871 ,  H01L27/11 ,  H01L27/1104

摘要： The semiconductor device comprises a gate interconnection 24a including a gate electrode formed over a semiconductor substrate 14 with a gate insulation film 22 formed therebetween; a first source/drain diffused layer 28 formed near the end of the gate interconnection 24a; a second source/drain diffused layer 34 formed remote from the gate interconnection 24a and the first source/drain diffused layer 28; and an insulation film 40 formed over the gate interconnection 24a, the first source/drain diffused layer 28 and the second source/drain diffused layer 34, and having a groove-shaped opening 42a formed in, which integrally exposes the gate interconnection 24a, one of the first source/drain diffused layer 28, and one of the second source/drain diffused layer 34; and a contact layer 48a buried in the groove-shaped opening 42a. The groove-shaped openings 42a for the contact layers 48a to be buried in can be formed without failure. Accordingly, it is possible to provide a semiconductor device which can realize the micronization without reliability decrease and fabrication yield decrease.

摘要翻译： 半导体器件包括栅极互连24a，栅极互连24a包括形成在半导体衬底14上的栅电极，其间形成有栅极绝缘膜22; 形成在栅极互连24a的端部附近的第一源极/漏极扩散层28; 远离栅极互连24a和第一源极/漏极扩散层28形成的第二源极/漏极扩散层34; 以及形成在栅极互连件24a上的绝缘膜40，第一源极/漏极扩散层28和第二源极/漏极扩散层34，并且具有形成在其中的沟槽形开口42a，其一体地露出栅极互连24 第一源极/漏极扩散层28中的一个和第二源极/漏极扩散层34中的一个; 以及埋在槽形开口部分41a中的接触层48a。 可以形成用于埋入的接触层48a的槽形开口部41a，而不会发生故障。 因此，可以提供一种能够实现微粉化而不降低可靠性并降低制造成品率的半导体器件。

公开(公告)号：US20050164129A1

公开(公告)日：2005-07-28

申请号：US11084017

申请日：2005-03-21

申请人： Takayoshi Minami

发明人： Takayoshi Minami

IPC分类号： G03F1/30 ,  G03F1/32 ,  G03F1/68 ,  G03F7/00 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49

CPC分类号： G03F1/30 ,  G03F1/32 ,  G03F1/36 ,  G03F1/70 ,  G03F7/203

摘要： A double exposure process is performed using a halftone phase shift mask (11) including gate patterns (1), assist patterns (2a) and (2b) with different resoluble line widths, and an assist pattern (2c) with a line width equal to or smaller than a resolution limit which are respectively inserted into portions in each of which a distance between the gate patterns (1) is large, and a Levenson phase shift mask (11) including shifter patterns (3) corresponding to the gate patterns (1) of the photomask 11. On this occasion, the assist patterns (2a), (2b), and (2c) are erased and only the gate patterns (1) are transferred. Consequently, when patterns are transferred by the double exposure process, a common depth of focus of the patterns is improved and highly uniform line widths are realized, which makes it possible to manufacture a highly reliable semiconductor device.

摘要翻译： 使用包括具有不同可分解线宽度的栅极图案（1），辅助图案（2a）和（2b）的半色调相移掩模（11）和具有线的辅助图案（2c）来执行双曝光处理 宽度等于或小于分辨率限制，其分别插入到栅极图案（1）之间的距离大的部分中，并且包括对应于栅极的移位器图案（3）的莱文森相移掩模（11） 在这种情况下，辅助图案（2a），（2b）和（2c）被擦除，并且只有栅极图案（1）被转印。 因此，当通过双重曝光处理传送图案时，图案的共同的深度焦点被改善并且实现了高度均匀的线宽，这使得可以制造高可靠性的半导体器件。

公开(公告)号：US06522003B1

公开(公告)日：2003-02-18

申请号：US09472833

申请日：1999-12-28

申请人： Takayoshi Minami ,  Osamu Tsuboi ,  Toshimi Ikeda ,  Masato Matsumiya ,  Kuninori Kawabata

发明人： Takayoshi Minami ,  Osamu Tsuboi ,  Toshimi Ikeda ,  Masato Matsumiya ,  Kuninori Kawabata

IPC分类号： H01L2348

CPC分类号： G03F7/70633 ,  G03F9/7084 ,  H01L23/522 ,  H01L23/544 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device characterized by comprising a first insulating film formed on the semiconductor substrate, a first wiring or mark formed on the first insulating film, an electrically isolated pattern formed under the first insulating film and below the first wiring or mark, a hole formed in the first insulating film to connect the first wiring or mark and the electrically isolated pattern, and a second insulating film for covering the first wiring or mark.

摘要翻译： 一种半导体器件，其特征在于，包括形成在所述半导体衬底上的第一绝缘膜，形成在所述第一绝缘膜上的第一布线或标记，形成在所述第一绝缘膜下方且在所述第一布线或标记下方的电隔离图案， 用于连接第一布线或标记和电隔离图案的第一绝缘膜，以及用于覆盖第一布线或标记的第二绝缘膜。

公开(公告)号：US07790335B2

公开(公告)日：2010-09-07

申请号：US11084017

申请日：2005-03-21

申请人： Takayoshi Minami

发明人： Takayoshi Minami

IPC分类号： G03F9/00 ,  G03F7/26

CPC分类号： G03F1/30 ,  G03F1/32 ,  G03F1/36 ,  G03F1/70 ,  G03F7/203

摘要： A double exposure process is performed using a halftone phase shift mask (11) including gate patterns (1), assist patterns (2a) and (2b) with different resoluble line widths, and an assist pattern (2c) with a line width equal to or smaller than a resolution limit which are respectively inserted into portions in each of which a distance between the gate patterns (1) is large, and a Levenson phase shift mask (11) including shifter patterns (3) corresponding to the gate patterns (1) of the photomask 11. On this occasion, the assist patterns (2a), (2b), and (2c) are erased and only the gate patterns (1) are transferred. Consequently, when patterns are transferred by the double exposure process, a common depth of focus of the patterns is improved and highly uniform line widths are realized, which makes it possible to manufacture a highly reliable semiconductor device.

摘要翻译： 使用包括具有不同可分解线宽度的栅极图案（1），辅助图案（2a）和（2b）的半色调相移掩模（11）和线宽度相等的辅助图案（2c）进行双曝光处理 或小于分别限制的分辨率限制，其分别插入到栅极图案（1）之间的距离较大的部分中，以及包括对应于栅极图案（1）的移位器图案（3）的列文森相移掩模（11） ）。在这种情况下，辅助图案（2a），（2b）和（2c）被擦除，并且只有栅极图案（1）被转印。 因此，当通过双重曝光处理传送图案时，图案的共同的深度焦点被改善并且实现了高度均匀的线宽，这使得可以制造高可靠性的半导体器件。

公开(公告)号：US20120220103A1

公开(公告)日：2012-08-30

申请号：US13463399

申请日：2012-05-03

申请人： Tomoyuki Yamada ,  Fumio Ushida ,  Shigetoshi Takeda ,  Tomoharu Awaya ,  Koji Banno ,  Takayoshi Minami

发明人： Tomoyuki Yamada ,  Fumio Ushida ,  Shigetoshi Takeda ,  Tomoharu Awaya ,  Koji Banno ,  Takayoshi Minami

IPC分类号： H01L21/78 ,  H01L21/283

CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

摘要翻译： 设置在半导体基板上的半导体器件包括：包含元件的元件区域，围绕元件区域的防潮框架;设置在防潮框架和半导体器件的外周边缘之间以及半导体衬底上的绝缘层 ，沿着外周缘延伸并设置在绝缘层中的第一金属线和设置在绝缘层中的槽。

公开(公告)号：US07971160B2

公开(公告)日：2011-06-28

申请号：US12017658

申请日：2008-01-22

申请人： Morimi Osawa ,  Takayoshi Minami ,  Satoru Asai

发明人： Morimi Osawa ,  Takayoshi Minami ,  Satoru Asai

IPC分类号： G06F17/50 ,  G03C5/00 ,  G03F1/00

CPC分类号： G03F1/36 ,  H01L27/0207

摘要： A method for creating a pattern on a photomask includes steps of recognizing a space between main patterns by using pattern data which indicate the main patterns to be adjacently transferred onto a wafer, determining a 1st rule about arrangement of an assist pattern on the photomask, the assist pattern being adjacent to the main patterns and not being transferred onto the wafer, estimating a depth of focus in the presence of the assist pattern among the main patterns, determining a 2nd rule about arrangement of the assist pattern on the photomask to improve the depth of focus in the presence of the 1st assist pattern among the main patterns in a group having one or more number of appearance times of the space between main patterns, and correcting the assist pattern on the photomask using the assist pattern data on the basis of the 2nd rule.

摘要翻译： 用于在光掩模上创建图案的方法包括通过使用指示要相邻转印到晶片上的主图案的图案数据来识别主图案之间的空间的步骤，确定关于光掩模上的辅助图案的布置的第一规则， 辅助图案与主图案相邻并且不被转印到晶片上，在主图案之中估计辅助图案的存在时估计焦深，确定关于在光掩模上的辅助图案的布置的第二规则以提高深度 在具有一个或多个主图案之间的空间的出现次数的组中的主要图案之中存在第一辅助图案的情况下，并且基于所述辅助图案数据来校正光掩模上的辅助图案 第二条规则

公开(公告)号：US06969580B2

公开(公告)日：2005-11-29

申请号：US10418042

申请日：2003-04-18

申请人： Takayoshi Minami

发明人： Takayoshi Minami

IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  G03F7/26

CPC分类号： H01L21/0273 ,  H01L21/28035 ,  H01L21/32139

摘要： A resist pattern of a resist film is formed by exposing the resist film using a gate electrode forming mask (a Levenson phase shift mask), and developing the resist film. An antireflection film is etched using the resist pattern as an etching mask, and the resist pattern and the antireflection film are trimmed. The manner of this trimming is not to etch a hard mask made of an inorganic material, but to etch the resist pattern and the antireflection film made of an organic material. Since a region consistent with a wiring pattern of the hard mask is covered by the resist pattern completely, breaking down and retraction of the wiring are prevented.

摘要翻译： 通过使用栅电极形成掩模（莱文生相移掩模）曝光抗蚀剂膜，并且形成抗蚀剂膜，形成抗蚀剂膜的抗蚀剂图案。 使用抗蚀剂图案作为蚀刻掩模蚀刻抗反射膜，并且修整抗蚀剂图案和抗反射膜。 这种修整的方式不是蚀刻由无机材料制成的硬掩模，而是蚀刻抗蚀剂图案和由有机材料制成的抗反射膜。 由于与硬掩模的布线图案一致的区域被抗蚀剂图案完全覆盖，所以防止布线的分解和缩回。