公开(公告)号：US5163178A

公开(公告)日：1992-11-10

申请号：US634454

申请日：1990-12-27

申请人： Takayuki Gomi ,  Minoru Nakamura ,  Hiroaki Anmo ,  Norikazu Chuchi ,  Hiroyuki Miwa ,  Akio Kayanuma ,  Koji Kobayashi

发明人： Takayuki Gomi ,  Minoru Nakamura ,  Hiroaki Anmo ,  Norikazu Chuchi ,  Hiroyuki Miwa ,  Akio Kayanuma ,  Koji Kobayashi

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8224 ,  H01L27/06 ,  H01L29/08 ,  H01L29/732 ,  H01L29/735

CPC分类号： H01L29/6625 ,  H01L21/8222 ,  H01L21/8224 ,  H01L29/735

摘要： A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter region are formed within the semiconductor substrate. A method of fabricating a semiconductor device comprises a step of forming a collector region of a second conduction type and an emitter region of a second conduction type in a lateral arrangement in a semiconductor substrate serving as a base region of a first conduction type by using a first mask provided with a pair of openings, and a step of forming heavily doped regions of the second conduction type so as to be connected respectively to the collector region and the emitter region by using a second mask provided with a pair of openings separated from each other by a distance greater than the distance between the openings of the first mask.

公开(公告)号：US5856228A

公开(公告)日：1999-01-05

申请号：US757335

申请日：1996-11-27

申请人： Hiroyuki Miwa ,  Shigeru Kanematsu ,  Takayuki Gomi ,  Hiroaki Anmo ,  Takashi Noguchi ,  Katsuyuki Kato ,  Hirokazu Ejiri ,  Norikazu Ouchi

发明人： Hiroyuki Miwa ,  Shigeru Kanematsu ,  Takayuki Gomi ,  Hiroaki Anmo ,  Takashi Noguchi ,  Katsuyuki Kato ,  Hirokazu Ejiri ,  Norikazu Ouchi

IPC分类号： H01L21/331 ,  H01L29/732

CPC分类号： H01L29/7322 ,  H01L29/66272 ,  Y10S148/01 ,  Y10S148/011

摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

摘要翻译： 一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。 半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

公开(公告)号：US5643806A

公开(公告)日：1997-07-01

申请号：US472869

申请日：1995-06-07

申请人： Hiroyuki Miwa ,  Shigeru Kanematsu ,  Takayuki Gomi ,  Hiroaki Anmo ,  Takashi Noguchi ,  Katsuyuki Kato ,  Hirokazu Ejiri ,  Norikazu Ouchi

发明人： Hiroyuki Miwa ,  Shigeru Kanematsu ,  Takayuki Gomi ,  Hiroaki Anmo ,  Takashi Noguchi ,  Katsuyuki Kato ,  Hirokazu Ejiri ,  Norikazu Ouchi

IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/7322 ,  H01L29/66272 ,  Y10S148/01 ,  Y10S148/011

摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

摘要翻译： 一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。 半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

公开(公告)号：US5541124A

公开(公告)日：1996-07-30

申请号：US477471

申请日：1995-06-07

申请人： Hiroyuki Miwa ,  Shigeru Kanematsu ,  Takayuki Gomi ,  Hiroaki Anmo ,  Takashi Noguchi ,  Katsuyuki Kato ,  Hirokazu Ejiri ,  Norikazu Ouchi

发明人： Hiroyuki Miwa ,  Shigeru Kanematsu ,  Takayuki Gomi ,  Hiroaki Anmo ,  Takashi Noguchi ,  Katsuyuki Kato ,  Hirokazu Ejiri ,  Norikazu Ouchi

IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/7322 ,  H01L29/66272 ,  Y10S148/01 ,  Y10S148/011

摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

摘要翻译： 一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。 半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

公开(公告)号：US4980748A

公开(公告)日：1990-12-25

申请号：US361554

申请日：1989-06-05

申请人： Hiroki Hozumi ,  Minoru Nakamura ,  Hiroyuki Miwa ,  Akio Kayanuma

发明人： Hiroki Hozumi ,  Minoru Nakamura ,  Hiroyuki Miwa ,  Akio Kayanuma

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/763 ,  H01L23/485 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/763 ,  H01L23/485 ,  H01L2924/0002

摘要： In a semiconductor device having trench-shaped element isolating regions formed in a semiconductor body and also a conductive layer extending on each element isolating region and connected to an impurity diffusion region of the semiconductor body, there is formed an insulator layer region between an extension of the conductive layer and the element isolating region, and the insulator layer region is buried in the surface portion of the semiconductor body. In such construction, the insulation space between the conductive layer and the semiconductor body can be increased while the distance between the element isolating region and the impurity diffusion region can be shortened to consequently diminish the parasitic capacitance between the conductive layer and the semiconductor body, hence attaining a faster operation in the semiconductor device. When the present invention is applied to a bipolar transistor integrated circuit, a superfast operation is ensured due to the reduction of the base-to-collector capacitance.

公开(公告)号：US5641692A

公开(公告)日：1997-06-24

申请号：US574363

申请日：1995-12-18

申请人： Hiroyuki Miwa ,  Hiroaki Anmo

发明人： Hiroyuki Miwa ,  Hiroaki Anmo

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L21/8249 ,  Y10S148/009

摘要： A method for producing a semiconductor device which decrease the number of processes at the time of producing BiCMOSLSI than the usual. Impurities are introduced into a semiconductor substrate under a second insulating film and a first electric conductive film utilizing a first insulating film and the first conductive film formed on the semiconductor substrate as masks. Therefore, it is able to perform concurrent introduction of impurities into the gate electrode, the source and the drain of the MOSFET, the base electrode of the bipolar transistor, the emitter and the collector contact of the lateral bipolar transistor, the outlet electrode of the capacitor, and the resistor, so that the number of process steps can be reduced.

摘要翻译： 一种半导体器件的制造方法，其减少生产BiCMOSLSI时的处理次数。 杂质在第二绝缘膜和第一导电膜的第二绝缘膜之下引入到半导体衬底中，并且第一导电膜利用第一绝缘膜和形成在半导体衬底上的第一导电膜作为掩模。 因此，能够同时引入杂质到栅电极，MOSFET的源极和漏极，双极晶体管的基极，横向双极晶体管的发射极和集电极接触， 电容器和电阻器，从而可以减少工艺步骤的数量。

公开(公告)号：US5324672A

公开(公告)日：1994-06-28

申请号：US966085

申请日：1992-10-23

申请人： Hiroaki Anmo ,  Hiroyuki Miwa

发明人： Hiroaki Anmo ,  Hiroyuki Miwa

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/732 ,  H01L21/265 ,  H01L29/70

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/732 ,  Y10S148/01

摘要： A bipolar transistor including a semiconductor layer formed on a semiconductor substrate; a base region formed at an upper portion of the semiconductor layer; a graft base region formed at the upper portion of the semiconductor layer so as to connect with a periphery of the base region; an emitter region formed at an upper portion of the base region; an offset insulating film formed on the base region around the emitter region; a collector buried region formed in the semiconductor layer below the base region; a collector drawn region formed in the semiconductor layer so as to connect with the collector buried region and be arranged on the side of the base region adjacent to an element isolating region; an emitter electrode formed on the offset insulating film so as to connect with the emitter region; an emitter insulating film formed so as to cover the emitter electrode; a base electrode formed so as to connect with the graft base region and contact with the emitter insulating film; and a collector electrode formed so as to connect with the collector drawn region.

摘要翻译： 一种双极晶体管，包括形成在半导体衬底上的半导体层; 形成在所述半导体层的上部的基极区域; 形成在所述半导体层的上部以与所述基底区域的周边连接的移植物基底区域; 形成在所述基极区域的上部的发射极区域; 形成在发射极区域周围的基极区域上的偏移绝缘膜; 集电极掩埋区域，形成在所述基极区域下方的所述半导体层中; 集电极引出区域，形成在所述半导体层中，以与所述集电极掩埋区域连接并且布置在所述基极区域与元件隔离区域相邻的一侧; 形成在所述偏移绝缘膜上以与所述发射极区域连接的发射电极; 形成为覆盖发射极的发射极绝缘膜; 形成为与移植物基底区域连接并与发射极绝缘膜接触的基极; 以及与集电极引出区域连接而形成的集电极。

公开(公告)号：US5783472A

公开(公告)日：1998-07-21

申请号：US787797

申请日：1997-01-23

申请人： Hiroyuki Miwa ,  Takayuki Gomi ,  Katsuyuki Kato

发明人： Hiroyuki Miwa ,  Takayuki Gomi ,  Katsuyuki Kato

IPC分类号： H01L29/73 ,  H01L21/22 ,  H01L21/331 ,  H01L21/38

CPC分类号： H01L29/7317 ,  H01L29/66265

摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

摘要翻译： 公开了能够形成窄尺寸扩散区域（例如基底宽度）的横向双极晶体管。 晶体管在扩散区域的宽度方向上没有散射。 通过在半导体部分中以大致均匀的浓度改变杂质扩散源并通过从杂质扩散源的扩散形成扩散区来减小发射极电阻。 双极晶体管具有SOI结构。 还公开了制造这种装置的方法。

公开(公告)号：US5629217A

公开(公告)日：1997-05-13

申请号：US319150

申请日：1994-10-06

申请人： Hiroyuki Miwa ,  Takayuki Gomi ,  Katsuyuki Kato

发明人： Hiroyuki Miwa ,  Takayuki Gomi ,  Katsuyuki Kato

IPC分类号： H01L29/73 ,  H01L21/22 ,  H01L21/331 ,  H01L21/38 ,  H01L21/26 ,  H01L21/265 ,  H01L21/306 ,  H01L21/479

CPC分类号： H01L29/7317 ,  H01L29/66265

摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

摘要翻译： 公开了能够形成窄尺寸扩散区域（例如基底宽度）的横向双极晶体管。 晶体管在扩散区域的宽度方向上没有散射。 通过在半导体部分中以大致均匀的浓度改变杂质扩散源并通过从杂质扩散源的扩散形成扩散区来减小发射极电阻。 双极晶体管具有SOI结构。 还公开了制造这种装置的方法。

公开(公告)号：US5414291A

公开(公告)日：1995-05-09

申请号：US189191

申请日：1994-01-31

申请人： Hiroyuki Miwa ,  Mamoru Shinohara ,  Takayuki Gomi ,  Tomotaka Fujisawa

发明人： Hiroyuki Miwa ,  Mamoru Shinohara ,  Takayuki Gomi ,  Tomotaka Fujisawa

IPC分类号： H01L27/06 ,  H01L27/02 ,  H01G4/06

CPC分类号： H01L27/0623

摘要： A semiconductor device comprising a MIS structure comprising a first electrically conductive film formed on an oxide film, a second electrically conductive film formed on at least a part of said first electrically conductive film, an insulator film formed on said second electrically conductive film, and a third electrically conductive film formed on said insulator film; and at least one electrode contact portion formed on said first electrically conductive film. A semiconductor device comprising a MIS capacitor having a diffusion layer inside the semiconductor substrate as a lower electrode with a first electrically conductive type being isolated using another diffusion layer having the opposite conductive type, and said another diffusion layer having the opposite conductive type being further isolated using a diffusion layer for isolation having the first conductive type and which is earthed. A BiCMOS semiconductor device comprising a resistor and an impurity source for the emitter and the emitter electrode for the bipolar transistor made of a same conductor layer, and further, a same conductor layer is provided as the contact electrode for the resistor and the gate for the MOS transistor. Also claimed are processes for fabricating the aforementioned semiconductor devices.

摘要翻译： 一种包括MIS结构的半导体器件，包括形成在氧化膜上的第一导电膜，形成在所述第一导电膜的至少一部分上的第二导电膜，形成在所述第二导电膜上的绝缘膜， 形成在所述绝缘膜上的第三导电膜; 以及形成在所述第一导电膜上的至少一个电极接触部分。 一种半导体器件，包括具有扩散层的MIS电容器，该半导体衬底内的扩散层作为具有第一导电类型的下电极，使用具有相反导电类型的另一扩散层来隔离，并且所述另一个具有相反导电类型的扩散层进一步隔离 使用具有第一导电类型并且接地的用于隔离的扩散层。 一种BiCMOS半导体器件，包括电阻器和用于由相同导体层制成的双极晶体管的发射极和发射极的杂质源，并且还提供相同的导体层作为电阻器的接触电极和用于 MOS晶体管。 还要求保护的是制造上述半导体器件的工艺。