公开(公告)号：US20060003825A1

公开(公告)日：2006-01-05

申请号：US11126277

申请日：2005-05-11

申请人： Takeshi Iwasaki ,  Hiroyasu Tamura ,  Noriyuki Shimoda ,  Tohru Murayama ,  Fuminori Sato ,  Junichi Yamanaka ,  Wataru Nakanishi ,  Hitoshi Iizawa ,  Yutaka Sudou

发明人： Takeshi Iwasaki ,  Hiroyasu Tamura ,  Noriyuki Shimoda ,  Tohru Murayama ,  Fuminori Sato ,  Junichi Yamanaka ,  Wataru Nakanishi ,  Hitoshi Iizawa ,  Yutaka Sudou

IPC分类号： A63F13/00

CPC分类号： A63F13/49 ,  A63F13/10 ,  A63F13/12 ,  A63F13/44 ,  A63F13/573 ,  A63F13/79 ,  A63F13/812 ,  A63F13/87 ,  A63F2300/1068 ,  A63F2300/407 ,  A63F2300/50 ,  A63F2300/534 ,  A63F2300/638 ,  A63F2300/8011 ,  A63F2300/8017

摘要： A match game processing method performs a match game having a plurality of stages by a plurality of players. By communicating among game apparatuses, a control unit controls to synchronize among the plays by the players in a virtual space, on a stage-by-stage basis. The game can be completed with a reduced waiting time of each player. Also, in a ghost match, the game proceeds in such a way that the control unit in the game apparatus performs a simple playback of a ghost data, according to the execution result obtained through the operation inputs from the player. Thus, in response to the execution result by the player, the ghost match is performed and the game time can be shortened.

摘要翻译： 匹配游戏处理方法通过多个玩家执行具有多个阶段的匹配游戏。 通过游戏装置之间的通信，控制单元控制在虚拟空间中的玩家在逐个的基础上在玩家之间进行同步。 游戏可以完成，每个玩家的等待时间缩短。 此外，在幽灵匹配中，游戏进行为使得游戏装置中的控制单元根据通过来自玩家的操作输入获得的执行结果执行重影数据的简单重放。 因此，响应于玩家的执行结果，执行幽灵匹配并且可以缩短游戏时间。

公开(公告)号：US20050193349A1

公开(公告)日：2005-09-01

申请号：US11069374

申请日：2005-03-01

申请人： Fuminori Sato ,  Tohru Murayama

发明人： Fuminori Sato ,  Tohru Murayama

IPC分类号： A63F13/00 ,  G06F17/00 ,  G06T17/05 ,  G06T19/00

CPC分类号： G06T15/20

摘要： The coordinate indicating objects are cross-shaped and aligned between the ball and cup. The virtual space has X axis from left to right, upward Y axis and Z axis toward depth direction. The coordinate indicating objects are arranged in a manner of check pattern on the X-Z coordinate. The Y-coordinate are set on the ground of course. The inclination indicating objects moves in descent direction between a pair of the coordinate indicating objects in a speed determined by the inclination value of the coordinate indicating objects adjacent in X or Z direction, that is, a difference of the Y-coordinate of the coordinate indicating objects. Therefore, clear expression is possible of inclination of inclined planes etc. without deteriorating natural atmosphere of a virtual space.

摘要翻译： 坐标指示对象是十字形的，并且在球和杯之间对准。 虚拟空间从左到右具有X轴，向上Y轴和Z轴朝向深度方向。 坐标指示对象以X-Z坐标上的检查图案的方式排列。 当然，Y坐标是在地面上设置的。 倾斜指示对象以由X或Z方向相邻的坐标的坐标的倾斜值确定的速度在一对坐标指示对象之间沿下降方向移动，即指示的坐标的Y坐标的差 对象 因此，在不使虚拟空间的自然气氛恶化的情况下，倾斜平面等倾斜的清晰表示是可能的。

公开(公告)号：US20070058478A1

公开(公告)日：2007-03-15

申请号：US11499692

申请日：2006-08-07

申请人： Tohru Murayama

发明人： Tohru Murayama

IPC分类号： G11C8/00

CPC分类号： G11C29/02 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012

摘要： An interface circuit includes: a first synchronizing circuit for synchronizing a signal having a delay equal to or more than a predetermined period with respect to a reference clock, with the reference clock; a second synchronizing circuit for synchronizing a signal having a delay less than the predetermined period with respect to the reference clock, with the reference clock; a delay determining circuit for outputting a determination signal based on a delay of the signal relative to the reference clock; a delay determination setting circuit for outputting a path setting signal that designates an output value of one of the first synchronizing circuit and the second synchronizing circuit based on a preset value; and a delay selecting circuit for selecting and outputting an output value of one of the first synchronizing circuit and the second synchronizing circuit based on one of the determination signal and the path setting signal.

摘要翻译： 一种接口电路包括：第一同步电路，用于将具有等于或大于预定周期的延迟的信号相对于参考时钟与参考时钟同步; 第二同步电路，用于将具有相对于参考时钟的延迟小于预定周期的信号与参考时钟同步; 延迟确定电路，用于基于所述信号相对于所述参考时钟的延迟来输出确定信号; 延迟确定设置电路，用于基于预设值输出指定第一同步电路和第二同步电路之一的输出值的路径设置信号; 以及延迟选择电路，用于基于所述确定信号和所述路径设置信号中的一个来选择和输出所述第一同步电路和所述第二同步电路之一的输出值。

公开(公告)号：US07376043B2

公开(公告)日：2008-05-20

申请号：US11499692

申请日：2006-08-07

申请人： Tohru Murayama

发明人： Tohru Murayama

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/02 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012

摘要： An interface circuit includes: a first synchronizing circuit for synchronizing a signal having a delay equal to or more than a predetermined period with respect to a reference clock, with the reference clock; a second synchronizing circuit for synchronizing a signal having a delay less than the predetermined period with respect to the reference clock, with the reference clock; a delay determining circuit for outputting a determination signal based on a delay of the signal relative to the reference clock; a delay determination setting circuit for outputting a path setting signal that designates an output value of one of the first synchronizing circuit and the second synchronizing circuit based on a preset value; and a delay selecting circuit for selecting and outputting an output value of one of the first synchronizing circuit and the second synchronizing circuit based on one of the determination signal and the path setting signal.

摘要翻译： 一种接口电路包括：第一同步电路，用于将具有等于或大于预定周期的延迟的信号相对于参考时钟与参考时钟同步; 第二同步电路，用于将具有相对于参考时钟的延迟小于预定周期的信号与参考时钟同步; 延迟确定电路，用于基于所述信号相对于所述参考时钟的延迟来输出确定信号; 延迟确定设置电路，用于基于预设值输出指定第一同步电路和第二同步电路之一的输出值的路径设置信号; 以及延迟选择电路，用于基于所述确定信号和所述路径设置信号中的一个来选择和输出所述第一同步电路和所述第二同步电路之一的输出值。

公开(公告)号：US06321291B1

公开(公告)日：2001-11-20

申请号：US09585837

申请日：2000-06-01

申请人： Tohru Murayama

发明人： Tohru Murayama

IPC分类号： G06F1200

CPC分类号： G11C29/50012 ,  G11C29/50

摘要： In order to precisely measure the speed of memory unit, the memory unit stores at least one bit data at a predetermined bit position at each memory word such that the logical value of the one bit data changes alternately in order of memory address. An address increment circuit, which is provided in a module including the memory unit, successively generates memory addresses which are applied to the memory. The address increment circuit increments a memory address in response to the output of the memory. The memory speed between two consecutive memory outputs is detected by measuring a pulse width of a pulse signal outputted from the memory unit. Thus, a relatively large delay otherwise caused at a buffer amplifier can effectively be compensated.

摘要翻译： 为了精确地测量存储器单元的速度，存储器单元在每个存储器字的预定位位置处存储至少一个位数据，使得一位数据的逻辑值以存储器地址的顺序交替改变。 提供在包括存储器单元的模块中的地址增加电路连续地生成应用于存储器的存储器地址。 地址增量电路响应于存储器的输出增加存储器地址。 通过测量从存储器单元输出的脉冲信号的脉冲宽度来检测两个连续存储器输出之间的存储器速度。 因此，可以有效地补偿在缓冲放大器处引起的相对较大的延迟。

公开(公告)号：US06115783A

公开(公告)日：2000-09-05

申请号：US911935

申请日：1997-08-15

申请人： Tohru Murayama

发明人： Tohru Murayama

IPC分类号： G01R31/317 ,  G01R31/28 ,  G11C11/413 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/822 ,  H01L27/04 ,  G06F12/00

CPC分类号： G11C29/50012 ,  G11C29/50

摘要： In order to precisely measure the speed of memory unit, the memory unit stores at least one bit data at a predetermined bit position at each memory word such that the logical value of the one bit data changes alternately in order of memory address. An address increment circuit, which is provided in a module including the memory unit, successively generates memory addresses which are applied to the memory. The address increment circuit increments a memory address in response to the output of the memory. The memory speed between two consecutive memory outputs is detected by measuring a pulse width of a pulse signal outputted from the memory unit. Thus, a relatively large delay otherwise caused at a buffer amplifier can effectively be compensated.

摘要翻译： 为了精确地测量存储器单元的速度，存储器单元在每个存储器字的预定位位置处存储至少一个位数据，使得一位数据的逻辑值以存储器地址的顺序交替改变。 提供在包括存储器单元的模块中的地址增加电路连续地生成应用于存储器的存储器地址。 地址增量电路响应于存储器的输出增加存储器地址。 通过测量从存储器单元输出的脉冲信号的脉冲宽度来检测两个连续存储器输出之间的存储器速度。 因此，可以有效地补偿在缓冲放大器处引起的相对较大的延迟。

公开(公告)号：US5828253A

公开(公告)日：1998-10-27

申请号：US823682

申请日：1997-03-25

申请人： Tohru Murayama

发明人： Tohru Murayama

IPC分类号： H03L7/00 ,  G06F1/04 ,  H03L3/00 ,  H03L7/08 ,  H03L7/095 ,  H03L7/14 ,  H03L7/10

CPC分类号： H03L3/00 ,  H03L7/08 ,  H03L7/095 ,  Y10S331/02

摘要： The invention provides a phase synchronization system which stops, when an input of a phase reference signal from the outside stops, oscillation of a voltage-controlled oscillator to achieve reduction in power consumption and can produce and output a system clock signal free from high frequency pulse noise from the voltage controlled oscillator. The system includes a phase comparator, a phase synchronization circuit including a low-pass filter and a voltage-controlled oscillation circuit, a clock detection circuit for detecting the clock signal from the outside, a phase coincidence discrimination circuit for discriminating a phase coincidence condition at the phase synchronization circuit, an AND gate, and a stop/start control circuit including a pair of flip-flop circuits. When the clock signal from the outside stops, oscillation of the voltage-controlled oscillation circuit is stopped with control information from the stop/start control circuit. When the input of the clock signal is resumed, a phase synchronization signal from the voltage-controlled oscillation circuit is outputted to the outside via the AND gate after phase coincidence is discriminated by the phase coincidence discrimination circuit.

摘要翻译： 本发明提供一种相位同步系统，当来自外部的相位参考信号的输入停止时，停止压控振荡器的振荡以实现功耗的降低，并且可以产生并输出没有高频脉冲的系统时钟信号 来自压控振荡器的噪声。 该系统包括相位比较器，包括低通滤波器和压控振荡电路的相位同步电路，用于检测来自外部的时钟信号的时钟检测电路，用于鉴别来自外部的相位一致条件的相位一致判别电路 相位同步电路，与门和包括一对触发器电路的停止/起动控制电路。 当来自外部的时钟信号停止时，通过来自停止/起动控制电路的控制信息停止压控振荡电路的振荡。 当时钟信号的输入被恢复时，来自压控振荡电路的相位同步信号通过相位一致判别电路鉴别出相位一致之后经由与门输出到外部。