公开(公告)号：US06768167B2

公开(公告)日：2004-07-27

申请号：US10442647

申请日：2003-05-21

申请人： Tatsuji Nagaoka ,  Tatsuhiko Fujihira ,  Yasuhiko Onishi

发明人： Tatsuji Nagaoka ,  Tatsuhiko Fujihira ,  Yasuhiko Onishi

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L27/0207 ,  H01L29/0696 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MIS semiconductor device has a greatly improved relation between the on-resistance and the switching time by forming trench completely through a p base region and positioning the trench adjacent to a gate electrode, and then implanting n-type impurity ions using the gate electrode as a mask to form a second drain region, which also serves as a drift region.

公开(公告)号：US06724042B2

公开(公告)日：2004-04-20

申请号：US09781066

申请日：2001-02-09

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L2976

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。

公开(公告)号：US07042046B2

公开(公告)日：2006-05-09

申请号：US10925407

申请日：2004-08-25

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L29/76 ,  H01L23/58

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

公开(公告)号：US07002205B2

公开(公告)日：2006-02-21

申请号：US10735501

申请日：2003-12-12

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。

公开(公告)号：US06674126B2

公开(公告)日：2004-01-06

申请号：US10073671

申请日：2002-02-11

申请人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： A01L29772

CPC分类号： H01L29/7802 ,  H01L29/0634

摘要： A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

摘要翻译： 半导体器件有助于在漏极漂移区周围的半导体芯片的部分中获得更高的击穿电压并且提高其雪崩耐受能力。 根据本发明的垂直MOSFET包括漏极层; 漏极层上的漏极漂移区，包括第一交替导电型层的漏极漂移区; 在漏极层和漏极漂移区域周围的击穿耐受区域（半导体芯片的外围区域），在MOSFET的导通状态基本上不提供电流路径的击穿承受区域，击穿耐受区域在断开状态 MOSFET，包括第二交替导电类型层的击穿耐受区域和栅极焊盘下方的下部区域，以及包括第三交变导电类型层的下部区域。

公开(公告)号：US06903418B2

公开(公告)日：2005-06-07

申请号：US10678941

申请日：2003-10-03

申请人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/772

CPC分类号： H01L29/7802 ,  H01L29/0634

摘要： A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

摘要翻译： 半导体器件有助于在漏极漂移区周围的半导体芯片的部分中获得更高的击穿电压并且提高其雪崩耐受能力。 根据本发明的垂直MOSFET包括漏极层; 漏极层上的漏极漂移区，包括第一交替导电型层的漏极漂移区; 在漏极层和漏极漂移区域周围的击穿耐受区域（半导体芯片的外围区域），在MOSFET的导通状态基本上不提供电流路径的击穿承受区域，击穿耐受区域在断开状态 MOSFET，包括第二交替导电类型层的击穿耐受区域和栅极焊盘下方的下部区域，以及包括第三交变导电类型层的下部区域。

公开(公告)号：US20050017292A1

公开(公告)日：2005-01-27

申请号：US10925407

申请日：2004-08-25

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L29/06 ,  H01L21/331 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。

公开(公告)号：US06696728B2

公开(公告)日：2004-02-24

申请号：US10099449

申请日：2002-03-15

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/7395 ,  H01L29/872

摘要： To provide a super-junction MOSFET reducing the tradeoff relation between the on-resistance and the breakdown voltage greatly and having a peripheral structure, which facilitates reducing the leakage current in the OFF-state thereof and stabilizing the breakdown voltage thereof. The vertical MOSFET according to the invention includes a drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (peripheral region) including a second alternating conductivity type layer around drain drift region, second alternating conductivity type layer being formed of layer-shaped vertically-extending n-type regions and layer-shaped vertically-extending p-type regions laminated alternately; an n-type region around second alternating conductivity type layer; and a p-type region formed in the surface portion of n-type region to reduce the leakage current in the OFF-state of the MOSFET.

摘要翻译： 为了提供一种超级结MOSFET，大大降低了导通电阻和击穿电压之间的折衷关系，并具有外围结构，这有助于减小其截止状态下的漏电流并稳定其击穿电压。 根据本发明的垂直MOSFET包括包括第一交变导电类型层的漏极漂移区; 包括漏极漂移区周围的第二交变导电型层的击穿耐受区域（周边区域），层叠的上下方向延伸的n型区域形成的第二交替导电型层和层叠的上下方向延伸的p型区域 交替; 围绕第二交变导电类型层的n型区域; 以及形成在n型区域的表面部分中的p型区域，以减小MOSFET的截止状态下的漏电流。

公开(公告)号：US06825565B2

公开(公告)日：2004-11-30

申请号：US10354890

申请日：2003-01-30

申请人： Yasuhiko Onishi ,  Tatsuji Nagaoka ,  Susumu Iwamoto ,  Takahiro Sato

发明人： Yasuhiko Onishi ,  Tatsuji Nagaoka ,  Susumu Iwamoto ,  Takahiro Sato

IPC分类号： H01L2348

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a drift region, which includes a first alternating conductivity type layer, and a peripheral region, which includes a second alternating conductivity type layer and a third alternating conductivity type layer in the surface portion of the peripheral region. The first layer includes first n-type regions and first p-type regions arranged alternately at a first pitch. The second layer is continuous with the first layer and includes second n-type regions and second p-type regions arranged alternately at the first pitch. The impurity concentration in the second layer is almost the same as the impurity concentration in the first layer. The third layer includes third n-type regions and third p-type regions arranged alternately at a second pitch. The third layer can be doped more lightly than the first and second alternating conductivity type layers. The second pitch can be the same as the first pitch or smaller.

摘要翻译： 半导体器件包括在周边区域的表面部分中包括第一交变导电型层和周边区域的漂移区域，其包括第二交变导电类型层和第三交变导电类型层。 第一层包括以第一间距交替布置的第一n型区域和第一p型区域。 第二层与第一层连续，并且包括以第一间距交替布置的第二n型区域和第二p型区域。 第二层中的杂质浓度几乎与第一层中的杂质浓度相同。 第三层包括以第二间距交替布置的第三n型区和第三p型区。 第三层可以比第一和第二交替导电类型层更轻地掺杂。 第二音调可以与第一音调相同或更小。

公开(公告)号：US06825537B2

公开(公告)日：2004-11-30

申请号：US10683868

申请日：2003-10-10

申请人： Susumu Iwamoto ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Susumu Iwamoto ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/7397

摘要： In a trench super junction semiconductor element having a parallel p-n junction layer 14 with n-drift regions 12 and p-partition regions 13, both extending in a depth direction, being alternately joined, a part 20 in a shape of a three-dimensional curved surface in the end portion of each of trenches is formed in a p-partition region 13. A section in the p-partition region 13 surrounding the part 20 in a shape of a three-dimensional curved surface of the end portion of each of the trenches is made as a p+-region 21 in which an impurity concentration is higher than that in a section thereunder so that an electric field is increased at a boundary between the p+-region 21 and the n-drift region 12, thereby lessening electric field concentration to the part 20 in a shape of a three-dimensional curved surface of the end portion of the trench. Moreover, the section in the p-partition region 13 surrounding the part 20 in a shape of a three-dimensional curved surface in the end portion of the trench can be formed wider than the section thereunder. This inhibits lowering in a breakdown voltage and, along with this, increases reliability of a gate insulator film.

摘要翻译： 在具有平行pn结层14的沟槽超结半导体元件中，其具有n个漂移区域12和p分隔区域13，两者都在深度方向上延伸交替地接合，形成为三维弯曲形状的部分20 每个沟槽的端部中的表面形成在p分隔区域13中。在p分隔区域13中的每个的端部的三维曲面形状的部分20周围的部分 沟槽被制成为其中杂质浓度高于其下段的杂质浓度的ap +区域21，使得在p +区域21和n-漂移区域12之间的边界处的电场增加 从而减小了沟槽端部的三维曲面形状的部分20的电场浓度。 此外，在沟槽端部的三维曲面形状的围绕部分20的p分隔区域13中的部分可以形成得比其下面的部分更宽。 这抑制了击穿电压的降低，并且与此同时增加了栅极绝缘膜的可靠性。