公开(公告)号：US09214587B2

公开(公告)日：2015-12-15

申请号：US13212395

申请日：2011-08-18

申请人： Kazuo Nishi ,  Yasushi Maeda ,  Ryosuke Motoyoshi ,  Yuji Oda ,  Kei Takahashi ,  Yoshiaki Ito ,  Tatsuji Nishijima

发明人： Kazuo Nishi ,  Yasushi Maeda ,  Ryosuke Motoyoshi ,  Yuji Oda ,  Kei Takahashi ,  Yoshiaki Ito ,  Tatsuji Nishijima

IPC分类号： H01L31/0224 ,  H01L31/075 ,  H01L31/02 ,  H01L31/05 ,  H01L31/046

CPC分类号： H01L31/075 ,  H01L31/02008 ,  H01L31/046 ,  H01L31/0504 ,  Y02E10/548

摘要： A photoelectric conversion module in which an output voltage defect is suppressed is obtained by forming in parallel over a substrate n number (n is a natural number) of integrated photoelectric conversion devices each including a plurality of cells that are connected in series, and electrically connecting in parallel n−1 number or less of integrated photoelectric conversion devices with normal electrical characteristics and excluding an integrated photoelectric conversion device with a characteristic defect such as a short-circuit between top and bottom electrodes or a leak current due to a structural defect or the like formed in a semiconductor layer or the like.

摘要翻译： 通过在基板上平行地形成n个（n为自然数）的集成光电转换装置，其中包含多个串联连接的单元，并且电连接，得到抑制输出电压缺陷的光电转换模块 并联n-1个或更少的具有正常电特性的集成光电转换装置，并且不包括具有诸如顶部和底部电极之间的短路的特性缺陷或由于结构缺陷引起的漏电流的集成光电转换装置 如在半导体层等中形成的。

公开(公告)号：US09059704B2

公开(公告)日：2015-06-16

申请号：US13477192

申请日：2012-05-22

申请人： Seiichi Yoneda ,  Jun Koyama ,  Yutaka Shionoiri ,  Masami Endo ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Kazuaki Ohshima

发明人： Seiichi Yoneda ,  Jun Koyama ,  Yutaka Shionoiri ,  Masami Endo ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Kazuaki Ohshima

IPC分类号： G06F1/00 ,  H03K19/177 ,  H03K19/173 ,  G06F3/06

CPC分类号： H03K19/173 ,  G06F1/3243 ,  G06F3/0679 ,  H03K19/17772 ,  Y02D10/152

摘要： An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.

摘要翻译： 目的是提供一种可编程逻辑器件，其被配置为即使在电源电压停止时仍保持逻辑电路的连接状态。 可编程逻辑器件包括可以改变其逻辑状态的运算电路; 配置改变电路改变运算电路的逻辑状态; 电源控制电路，控制对所述运算电路的电源电压供给; 存储关于逻辑状态的数据的状态存储电路和关于运算电路的电源电压的状态的数据; 以及算术状态控制电路，根据存储在状态存储电路中的数据控制配置改变电路和电源控制电路。 在配置改变电路和每个运算电路之间设置有在氧化物半导体层中形成沟道形成区的晶体管。

公开(公告)号：US08922182B2

公开(公告)日：2014-12-30

申请号：US12956491

申请日：2010-11-30

申请人： Kei Takahashi ,  Yoshiaki Ito ,  Hiroki Inoue ,  Tatsuji Nishijima

发明人： Kei Takahashi ,  Yoshiaki Ito ,  Hiroki Inoue ,  Tatsuji Nishijima

IPC分类号： G05F1/00 ,  H01L27/12 ,  H01L29/786 ,  H02M3/155

CPC分类号： H02M3/156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869 ,  H02M3/155

摘要： A DC converter circuit having high reliability is provided. The DC converter circuit includes: an inductor configured to generate electromotive force in accordance with a change in flowing current; a transistor including a gate, a source, and a drain, which is configured to control generation of the electromotive force in the inductor by being on or off; a rectifier in a conducting state when the transistor is off; and a control circuit configured to control on and off of the transistor. The transistor includes an oxide semiconductor layer whose hydrogen concentration is less than or equal to 5×1019 atoms/cm3 as a channel formation layer.

摘要翻译： 提供了具有高可靠性的DC转换器电路。 DC转换器电路包括：电感器，被配置为根据流动电流的变化产生电动势; 包括栅极，源极和漏极的晶体管，其被配置为通过导通或关断来控制电感器中的电动势的产生; 当晶体管截止时处于导通状态的整流器; 以及被配置为控制晶体管的导通和截止的控制电路。 晶体管包括作为沟道形成层的氢浓度小于或等于5×1019原子/ cm3的氧化物半导体层。

公开(公告)号：US08311315B2

公开(公告)日：2012-11-13

申请号：US13067782

申请日：2011-06-27

申请人： Teppei Oguni ,  Tatsuji Nishijima ,  Akiharu Miyanaga

发明人： Teppei Oguni ,  Tatsuji Nishijima ,  Akiharu Miyanaga

IPC分类号： G06K9/00 ,  H04N7/18

CPC分类号： G01N21/95692 ,  G06T7/0004 ,  G06T7/90 ,  G06T2207/30148

摘要： A color image of an inspection object is taken by an imaging means capable of taking a color image to obtain color information of an RGB color space. A gray-scale image of a color component of the RGB color space or another color space is generated, and the inspection object is detected by a pattern recognition technique. Alternatively, a binary image is generated from the generated gray-scale image, and the inspection object is detected by performing pattern recognition on the binary image. Color data of a pixel occupied by the detected inspection object is compared with color data of a non-defective inspection object which is previously prepared to judge whether or not the inspection object is defective. In addition, this judgment result is reflected in another manufacturing step through a network and product quality is improved.

摘要翻译： 检查对象的彩色图像由能够拍摄彩色图像的成像装置获取以获得RGB颜色空间的颜色信息。 生成RGB颜色空间或其他颜色空间的颜色分量的灰度图像，并且通过模式识别技术检测检查对象。 或者，从生成的灰度图像生成二值图像，并且通过对二值图像执行模式识别来检测检查对象。 将检测到的检查对象占据的像素的颜色数据与预先准备好判断检查对象是否有缺陷的无缺陷检查对象的颜色数据进行比较。 此外，这种判断结果反映在通过网络的另一制造步骤中，并且产品质量得到改善。

公开(公告)号：US20060210142A1

公开(公告)日：2006-09-21

申请号：US11334476

申请日：2006-01-19

申请人： Teppei Oguni ,  Tatsuji Nishijima ,  Akiharu Miyanaga

发明人： Teppei Oguni ,  Tatsuji Nishijima ,  Akiharu Miyanaga

IPC分类号： H04N7/18 ,  G06K9/00

CPC分类号： G01N21/95692 ,  G06T7/0004 ,  G06T7/90 ,  G06T2207/30148

摘要： A color image of an inspection object is taken by an imaging means capable of taking a color image to obtain color information of an RGB color space. A gray-scale image of a color component of the RGB color space or another color space is generated, and the inspection object is detected by a pattern recognition technique. Alternatively, a binary image is generated from the generated gray-scale image, and the inspection object is detected by performing pattern recognition on the binary image. Color data of a pixel occupied by the detected inspection object is compared with color data of a non-defective inspection object which is previously prepared to judge whether or not the inspection object is defective. In addition, this judgment result is reflected in another manufacturing step through a network and product quality is improved.

摘要翻译： 检查对象的彩色图像由能够拍摄彩色图像的成像装置获取以获得RGB颜色空间的颜色信息。 生成RGB颜色空间或其他颜色空间的颜色分量的灰度图像，并且通过模式识别技术检测检查对象。 或者，从生成的灰度图像生成二值图像，并且通过对二值图像执行模式识别来检测检查对象。 将检测到的检查对象占据的像素的颜色数据与预先准备好判断检查对象是否有缺陷的无缺陷检查对象的颜色数据进行比较。 此外，这种判断结果反映在通过网络的另一制造步骤中，并且产品质量得到改善。

公开(公告)号：US08698521B2

公开(公告)日：2014-04-15

申请号：US13472018

申请日：2012-05-15

申请人： Tatsuji Nishijima

发明人： Tatsuji Nishijima

IPC分类号： H03K19/0944

CPC分类号： H01L29/7869 ,  H03K19/0944 ,  H03K19/20

摘要： A semiconductor device in which a transistor using an oxide semiconductor containing In, Zn, or the like for a channel region can be driven like a p-channel transistor is provided. The semiconductor device includes a transistor and an inverter, wherein an output of the inverter is input to a gate of the transistor, a channel region of the transistor includes an oxide semiconductor film containing In, Zn, or Sn, and each channel region of transistors in the inverter contains silicon. When a high voltage is input to the inverter, a low voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned off. When a low is input to the inverter, a high voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned on.

摘要翻译： 提供一种半导体器件，其中可以像p沟道晶体管一样驱动使用含有沟道区的In，Zn等的氧化物半导体的晶体管。 半导体器件包括晶体管和反相器，其中反相器的输出被输入到晶体管的栅极，晶体管的沟道区包括含有In，Zn或Sn的氧化物半导体膜，以及晶体管的每个沟道区 在变频器内含硅。 当高电压输入到逆变器时，从反相器输出低电压并输入到晶体管的栅极，使得晶体管截止。 当反相器输入低电平时，从反相器输出高电压并输入到晶体管的栅极，使晶体管导通。

公开(公告)号：US08581625B2

公开(公告)日：2013-11-12

申请号：US13463084

申请日：2012-05-03

申请人： Seiichi Yoneda ,  Tatsuji Nishijima

发明人： Seiichi Yoneda ,  Tatsuji Nishijima

IPC分类号： H03K19/173

CPC分类号： H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K19/0008 ,  H03K19/17736 ,  H03K19/17744

摘要： An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device.

摘要翻译： 目的是提供一种具有通过可编程开关彼此连接的逻辑块的可编程逻辑器件，其中可编程开关的特征在于结合在其中的氧化物半导体晶体管。 氧化物半导体晶体管的非常低的截止电流由于其保持与氧化物半导体晶体管连接的晶体管的栅极的电位的高能力而提供作为非易失性存储器的功能。 氧化物半导体晶体管用作非易失性存储器的能力允许用于控制逻辑块的连接的配置数据即使在没有电源电位的情况下也被维持。 因此，可以省略在设备启动时的配置数据的重写处理，这有助于降低设备的功耗。

公开(公告)号：US08476927B2

公开(公告)日：2013-07-02

申请号：US13453147

申请日：2012-04-23

申请人： Tatsuji Nishijima

发明人： Tatsuji Nishijima

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H01L27/11803 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/17772

摘要： An object of the present invention is to provide a programmable logic device which has short start-up time after supply of power is stopped, is highly integrated, and operates with low power. In a programmable logic device including an input/output block, a plurality of logic blocks each including a logic element, and a wiring connecting the plurality of logic blocks, the logic element has a configuration memory for holding configuration data and a look-up table including a selection circuit. The configuration memory includes a plurality of memory elements each of which includes a transistor whose channel region is in an oxide semiconductor film and an arithmetic circuit provided between the transistor and the selection circuit. Configuration data is selectively changed and output by the selection circuit in accordance with an input signal.

公开(公告)号：US08439270B2

公开(公告)日：2013-05-14

申请号：US12558156

申请日：2009-09-11

申请人： Tatsuji Nishijima

发明人： Tatsuji Nishijima

IPC分类号： G06K19/06 ,  H01L29/66 ,  H02H3/20

CPC分类号： H01L27/0251 ,  G06K19/0707 ,  G06K19/0712 ,  G06K19/0715 ,  G06K19/07749

摘要： In a wireless tag with which a wireless communication system whose electric power of a carrier wave from a R/W is high, an overvoltage protection circuit is provided to prevent from generating excessive electric power in the wireless tag when the wireless tag receives excessive electric power. However, as noise is generated by operation of the overvoltage protection circuit, an error of reception occurs in receiving a signal whose modulation factor is small. To solve the problem, the maximum value of generated voltage in the wireless tag is held in a memory circuit after the overvoltage protection circuit operates, then the overvoltage protection circuit is controlled in accordance with the maximum value of generated voltage. The voltages at which the overvoltage protection circuit starts and stops operating are different from each other, and hysteresis occurs between the timing when the overvoltage protection circuit starts and stops operating.

摘要翻译： 在R / W的载波功率高的无线通信系统的无线标签中，提供过电压保护电路，以防止当无线标签接收到过大的电力时在无线标签中产生过大的电力 。 然而，由于通过过电压保护电路的工作产生噪声，因此在接收调制度小的信号时发生接收错误。 为了解决这个问题，在过电压保护电路工作之后，将无线标签中产生的电压的最大值保持在存储电路中，然后根据产生的电压的最大值来控制过电压保护电路。 过电压保护电路的起动和停止运行的电压彼此不同，在过电压保护电路的启动停止运行的定时之间产生滞后。

公开(公告)号：US08184923B2

公开(公告)日：2012-05-22

申请号：US11095479

申请日：2005-04-01

申请人： Masahiko Hayakawa ,  Tatsuji Nishijima

发明人： Masahiko Hayakawa ,  Tatsuji Nishijima

IPC分类号： G06K9/40

CPC分类号： G09G3/006 ,  G02F1/1309 ,  G09G2360/147

摘要： In the case where a digital camera is used for evaluating a display quality of an image display panel, moire is generated due to a shift of a pixel pitch between a pixel of a panel and a pixel of a digital camera, and thus, a great influence is given as measurement deviation. The present invention carries out a panel display quality evaluation at low cost and short time with relieved influence of moire by treating a value, which is obtained by recognizing a coordinate of a panel pixel in a shot image based on an image for detecting a coordinate and positional information thereof with high accuracy and by calculating average luminance by panel pixel unit based on a center position of a coordinate, as representative luminance in each pixel of the panel, in a panel evaluation method of shooting an image display panel with a digital camera.

摘要翻译： 在数字照相机用于评估图像显示面板的显示质量的情况下，由于面板的像素与数码相机的像素之间的像素间距偏移而产生莫尔条纹，因此， 影响作为测量偏差。 本发明通过处理通过基于用于检测坐标的图像来识别拍摄图像中的面板像素的坐标而获得的值，以低成本和短时间执行面板显示质量评估，并且以莫干的影响来减轻影响，并且 在通过数字照相机拍摄图像显示面板的面板评估方法中，基于坐标的中心位置作为面板的每个像素中的代表性亮度，通过面板像素单元计算平均亮度。