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公开(公告)号：US07319575B2
公开(公告)日：2008-01-15
申请号：US11288323
申请日：2005-11-29
CPC分类号： H03F1/52 , H01L27/0266
摘要： This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.
摘要翻译： 本发明提供一种半导体器件，其中可以以小的裸片面积实现ESD保护电路和终端电路。 具有ESD保护功能的PMOS晶体管被放置在从信号端到输入缓冲器的线路上的信号节点和电源电压节点之间。 此外，放置电压发生器电路以向PMOS晶体管的栅极提供参考电压。 通过由电压发生器电路控制的参考电压，设置PMOS晶体管的源极漏极电阻。 由此，除了ESD保护功能之外，还可以使PMOS晶体管起到终端电阻的作用，该电阻的电阻可以适应于传输线的特性阻抗，例如连接到信号端。
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2.发明申请公开(公告)号：US20050207228A1
公开(公告)日：2005-09-22
申请号：US11030067
申请日：2005-01-07
CPC分类号： G11B5/02 , B82Y10/00 , B82Y25/00 , G11B5/022 , G11B2005/0013 , G11B2005/3996 , H03K17/6872 , H03K2217/0036
摘要： The present invention provides a semiconductor integrated circuit capable of reducing a circuit area and a magnetic storage device using the same. The circuit in the present invention is provided with a single-stage output transistor for supplying write current to a magnetic head, a current source for outputting reference current of the write current, a diode-connected NMOS transistor for converting the current to gate voltage and having a certain device size ratio to the output transistor, a regulator circuit for transmitting gate voltage of the NMOS transistor and reducing output impedance, and a CMOS circuit for setting power supply voltage to an output of the regulator circuit and controlling the gate voltage of the output transistor. Then, this circuit is applied as a write circuit in a magnetic storage device.
摘要翻译： 本发明提供能够减少电路面积的半导体集成电路和使用该半导体集成电路的磁存储装置。 本发明的电路设置有用于向磁头提供写入电流的单级输出晶体管，用于输出写入电流的参考电流的电流源，用于将电流转换为栅极电压的二极管连接的NMOS晶体管，以及 与输出晶体管具有一定的器件尺寸比，用于传输NMOS晶体管的栅极电压并降低输出阻抗的调节器电路，以及用于将电源电压设置到调节器电路的输出并控制调节器电路的栅极电压的CMOS电路 输出晶体管。 然后，该电路作为写入电路应用于磁存储装置。
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公开(公告)号：US07417818B2
公开(公告)日：2008-08-26
申请号：US11342828
申请日：2006-01-31
IPC分类号： G11B5/02
摘要： A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zs and a magnetic head, the transmission lines are formed so that the characteristic impedances Z1, Zn−1, and Zn (n≧2) thereof on the output driver side are higher than those on the magnetic recording head side (Z1>Zn−1>Zn), and the impedance Zs of the output driver is equal to or higher than the characteristic impedance Z1 of the transmission line.
摘要翻译： 提供了能够通过容易地调整写入电流脉冲的过冲来减小写入电路的尺寸和功耗的磁记录装置。 具有不同特性阻抗的两条或更多条传输线被提供在具有阻抗Z S s的输出驱动器和磁头之间，传输线形成为使得特性阻抗Z 1 = 2）高于磁记录头侧（Z 1 。
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4.发明授权公开(公告)号：US07046468B2
公开(公告)日：2006-05-16
申请号：US11030067
申请日：2005-01-07
IPC分类号： G11B5/02
CPC分类号： G11B5/02 , B82Y10/00 , B82Y25/00 , G11B5/022 , G11B2005/0013 , G11B2005/3996 , H03K17/6872 , H03K2217/0036
摘要： The present invention provides a semiconductor integrated circuit capable of reducing a circuit area and a magnetic storage device using the same. The circuit in the present invention is provided with a single-stage output transistor for supplying write current to a magnetic head, a current source for outputting reference current of the write current, a diode-connected NMOS transistor for converting the current to gate voltage and having a certain device size ratio to the output transistor, a regulator circuit for transmitting gate voltage of the NMOS transistor and reducing output impedance, and a CMOS circuit for setting power supply voltage to an output of the regulator circuit and controlling the gate voltage of the output transistor. Then, this circuit is applied as a write circuit in a magnetic storage device.
摘要翻译： 本发明提供能够减少电路面积的半导体集成电路和使用该半导体集成电路的磁存储装置。 本发明的电路设置有用于向磁头提供写入电流的单级输出晶体管，用于输出写入电流的参考电流的电流源，用于将电流转换为栅极电压的二极管连接的NMOS晶体管，以及 与输出晶体管具有一定的器件尺寸比，用于传输NMOS晶体管的栅极电压并降低输出阻抗的调节器电路，以及用于将电源电压设置到调节器电路的输出并控制调节器电路的栅极电压的CMOS电路 输出晶体管。 然后，该电路作为写入电路应用于磁存储装置。
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5.发明授权Signal transmission circuit, signal output circuit and termination method of signal transmission circuit 有权信号传输电路，信号输出电路和信号传输电路的终端方法公开(公告)号：US07373114B2
公开(公告)日：2008-05-13
申请号：US11030063
申请日：2005-01-07
IPC分类号： H04B1/44
CPC分类号： H04B3/02 , H04L25/0282
摘要： This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a signal output circuit does not match a characteristic impedance of a transmission path. On a signal transmission circuit composed of a transmission path, a signal output circuit connected to a transmitting node of the transmission path, and a signal receiver circuit connected to a receiving node of the signal transmission path, in order to prevent the re-reflection of an output signal of a signal output unit at the transmitting node via the receiving node, a correction current generator unit is provided for outputting correction current with a predetermined current amount and at a predetermined timing set in a current amount/timing control section, to the transmitting node.
摘要翻译： 本发明提供信号传输电路，信号输出电路和信号传输电路的终止方法，该信号传输电路即使在信号输出电路的阻抗发生时也能防止在传输路径的发射节点处的信号的再反射 不符合传输路径的特性阻抗。 在由传输路径组成的信号传输电路，连接到传输路径的发送节点的信号输出电路以及连接到信号传输路径的接收节点的信号接收器电路中，以防止重新反射 经由接收节点在发送节点处的信号输出单元的输出信号，提供校正电流发生器单元，用于以预定电流量和在当前量/定时控制部分中设置的预定定时输出校正电流， 发送节点。
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公开(公告)号：US20060203372A1
公开(公告)日：2006-09-14
申请号：US11342828
申请日：2006-01-31
IPC分类号： G11B5/02
摘要： A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zs and a magnetic head, the transmission lines are formed so that the characteristic impedances Z1, Zn−1, and Zn (n≧2) thereof on the output driver side are higher than those on the magnetic recording head side (Z1>Zn−1>Zn), and the impedance Zs of the output driver is equal to or higher than the characteristic impedance Z1 of the transmission line.
摘要翻译： 提供了能够通过容易地调整写入电流脉冲的过冲来减小写入电路的尺寸和功耗的磁记录装置。 具有不同特性阻抗的两条或更多条传输线被提供在具有阻抗Z S s的输出驱动器和磁头之间，传输线形成为使得特性阻抗Z 1 = 2）高于磁记录头侧（Z 1 。
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公开(公告)号：US20060158802A1
公开(公告)日：2006-07-20
申请号：US11288323
申请日：2005-11-29
IPC分类号： H02H9/00
CPC分类号： H03F1/52 , H01L27/0266
摘要： This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source-drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.
摘要翻译： 本发明提供一种半导体器件，其中可以以小的裸片面积实现ESD保护电路和终端电路。 具有ESD保护功能的PMOS晶体管被放置在从信号端到输入缓冲器的线路上的信号节点和电源电压节点之间。 此外，放置电压发生器电路以向PMOS晶体管的栅极提供参考电压。 通过由电压发生器电路控制的参考电压，设置PMOS晶体管的源极 - 漏极电阻。 由此，除了ESD保护功能之外，还可以使PMOS晶体管起到终端电阻的作用，该电阻的电阻可以适应于传输线的特性阻抗，例如连接到信号端。
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8.发明申请Signal transmission circuit, signal output circuit and termination method of signal transmission circuit 有权信号传输电路，信号输出电路和信号传输电路的终端方法公开(公告)号：US20050208902A1
公开(公告)日：2005-09-22
申请号：US11030063
申请日：2005-01-07
CPC分类号： H04B3/02 , H04L25/0282
摘要： This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a signal output circuit does not match a characteristic impedance of a transmission path. On a signal transmission circuit composed of a transmission path, a signal output circuit connected to a transmitting node of the transmission path, and a signal receiver circuit connected to a receiving node of the signal transmission path, in order to prevent the re-reflection of an output signal of a signal output unit at the transmitting node via the receiving node, a correction current generator unit is provided for outputting correction current with a predetermined current amount and at a predetermined timing set in a current amount/timing control section, to the transmitting node.
摘要翻译： 本发明提供信号传输电路，信号输出电路和信号传输电路的终止方法，该信号传输电路即使在信号输出电路的阻抗发生时也能防止在传输路径的发射节点处的信号的再反射 不符合传输路径的特性阻抗。 在由传输路径组成的信号传输电路，连接到传输路径的发送节点的信号输出电路以及连接到信号传输路径的接收节点的信号接收器电路中，以防止重新反射 经由接收节点在发送节点处的信号输出单元的输出信号，提供校正电流发生器单元，用于以预定电流量和在当前量/定时控制部分中设置的预定定时输出校正电流， 发送节点。
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9.发明授权Low-offset input circuit including amplifier circuit to correct circuit characteristics to cancel offset of the input circuit 失效低失调输入电路包括放大器电路，用于校正电路特性以消除输入电路的偏移公开(公告)号：US07795944B2
公开(公告)日：2010-09-14
申请号：US12183080
申请日：2008-07-31
IPC分类号： H03L5/00
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45744 , H03F3/45968 , H03F2203/45212 , H03F2203/45702
摘要： In a signal transmission system where an influence of the circuit characteristic variation of an input circuit on signal receiving operation cannot be ignored, there is provided a method of realizing a low-offset input circuit which is capable of conducting high-speed operation and always continuing signal receiving operation without increasing the number of terminals of a semiconductor integrated circuit and without the necessity of providing additional signal observing means and variation adjustment amount calculating means to the external of the semiconductor integrated circuit. In a signal receiver circuit having an input circuit, an automatic zero amplifier, an analog/digital converter circuit, an encoder circuit, and a signal holding circuit, an output error signal of the input circuit is amplified by the automatic zero amplifier, and the signal is digitalized or the digitalized signal is encoded as the occasion demands, and held by the holding circuit, and the circuit characteristic variation of the input circuit is adjusted by the held signal.
摘要翻译： 在输入电路对信号接收操作的电路特性变化的影响不能忽略的信号传输系统中，提供了一种实现低偏移输入电路的方法，该低失调输入电路能够进行高速操作并且总是继续 信号接收操作而不增加半导体集成电路的端子数量，而不需要向半导体集成电路的外部提供额外的信号观测装置和变化调整量计算装置。 在具有输入电路，自动零放大器，模拟/数字转换器电路，编码器电路和信号保持电路的信号接收器电路中，输入电路的输出误差信号由自动零放大器放大， 信号被数字化或数字化信号根据场合需要编码并由保持电路保持，并且通过保持信号调整输入电路的电路特性变化。
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公开(公告)号：US08358708B2
公开(公告)日：2013-01-22
申请号：US12453980
申请日：2009-05-28
IPC分类号： H04L7/00
CPC分类号： H03F3/45475 , H03F3/24 , H03F3/3028 , H03F3/45183 , H03F3/45605 , H03F3/45977 , H03F2200/411 , H03F2200/537 , H03F2203/45212 , H03F2203/45674 , H03F2203/45702 , H03F2203/45726
摘要： A low offset input circuit and a signal transmission system which can accommodate a high-speed interface and achieve reduction of an offset voltage are provided. An offset voltage compensating circuit block 103 having an input circuit block 108 including an input circuit 104 and an adder-subtractor circuit block 105, switches 108, 109, a detecting circuit block 106, and an adjusting and holding circuit block 107 is provided. To compensate for an offset voltage of the input circuit block 102, an offset voltage of the input circuit block 102 is detected at the detecting circuit block 106 by turning on the switches 108, 109, and the detected offset voltage is held in the adjusting and holding circuit block 107, and negative feedback of the held offset voltage to the adder-subtractor circuit block 105 is performed. Thereby, signals Vop, Von having compensated offset voltages are outputted from the input circuit block 102.
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