公开(公告)号：US5656517A

公开(公告)日：1997-08-12

申请号：US473837

申请日：1995-06-07

申请人： Taylor R. Efland ,  Roy C. Jones, III ,  Oh-Kyong Kwon ,  Michael C. Smayling ,  Satwinder Malhi ,  Wai Tung Ng

发明人： Taylor R. Efland ,  Roy C. Jones, III ,  Oh-Kyong Kwon ,  Michael C. Smayling ,  Satwinder Malhi ,  Wai Tung Ng

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/7802 ,  H01L29/42368

摘要： A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of predetermined size and separated by predetermined distances; and a plurality of source contact windows alternating with the backgate contact segments so that a narrow source contact region is formed of alternating source contact and backgate contact material. A DMOS transistor embodying the source region including the backgate contact segments and windowed source contacting regions of the invention is disclosed. An integrated circuit providing an array of DMOS transistors having the improved source regions of the invention is disclosed.Other devices, systems and methods are also disclosed.

摘要翻译： 公开了一种具有减小的面积和降低的多晶硅窗口宽度要求的源单元，用于DMOS晶体管中的源极区域，包括：设置在半导体衬底上的半导体材料的源极区域; 多个预定尺寸的后门接触片段并隔开预定距离; 以及多个源极接触窗与后盖接触片交替，使得窄的源极接触区域由交替的源极接触和后盖接触材料形成。 公开了体现源区域的DMOS晶体管，其包括本发明的背栅接触段和窗口源极接触区域。 公开了提供具有本发明改进的源极区域的DMOS晶体管阵列的集成电路。 还公开了其他装置，系统和方法。

公开(公告)号：US5585657A

公开(公告)日：1996-12-17

申请号：US358631

申请日：1994-12-19

申请人： Taylor R. Efland ,  Roy C. Jones, III ,  Oh-Kyong Kwon ,  Michael C. Smayling ,  Satwinder Malhi ,  Wai T. Ng

发明人： Taylor R. Efland ,  Roy C. Jones, III ,  Oh-Kyong Kwon ,  Michael C. Smayling ,  Satwinder Malhi ,  Wai T. Ng

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/72 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/7802 ,  H01L29/42368

摘要： A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of predetermined size and separated by predetermined distances; and a plurality of source contact windows alternating with the backgate contact segments so that a narrow source contact region is formed of alternating source contact and backgate contact material. A DMOS transistor embodying the source region including the backgate contact segments and windowed source contacting regions of the invention is disclosed. An integrated circuit providing an array of DMOS transistors having the improved source regions of the invention is disclosed.Other devices, systems and methods are also disclosed.

摘要翻译： 公开了一种具有减小的面积和降低的多晶硅窗口宽度要求的源单元，用于DMOS晶体管中的源极区域，包括：设置在半导体衬底上的半导体材料的源极区域; 多个预定尺寸的后门接触片段并隔开预定距离; 以及多个源极接触窗与后盖接触片交替，使得窄的源极接触区域由交替的源极接触和后盖接触材料形成。 公开了体现源区域的DMOS晶体管，其包括本发明的背栅接触段和窗口源极接触区域。 公开了提供具有本发明改进的源极区域的DMOS晶体管阵列的集成电路。 还公开了其他装置，系统和方法。

公开(公告)号：US5306652A

公开(公告)日：1994-04-26

申请号：US815732

申请日：1991-12-30

申请人： Oh-Kyong Kwon ,  Taylor R. Efland ,  Satwinder Malhi ,  Wai T. Ng

发明人： Oh-Kyong Kwon ,  Taylor R. Efland ,  Satwinder Malhi ,  Wai T. Ng

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66681 ,  H01L29/7801 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  Y10S148/096

摘要： A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12) . A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).

摘要翻译： 晶体管（10）在第一导电类型的半导体衬底（12）上具有第二导电类型的薄外延层（14）。 形成第二导电类型的漂移区（24），延伸穿过薄外延层（14）到衬底（12）。 在漂移区（24）上形成厚的绝缘体层（26）。 第一导电类型的IGFET体（28）形成在漂移区（24）附近。 第二导电类型的源极区域（34）形成在IGFET主体（28）内并且与漂移区域（24）间隔开，以限定IGFET体（28）内的沟道区域（40）。 导电栅极（32）被绝缘地设置在IGFET主体（28）上并且从源极区域（34）延伸到厚的绝缘体层（26）。 在漂移区（24）附近形成漏区（36）。

公开(公告)号：US5406110A

公开(公告)日：1995-04-11

申请号：US191228

申请日：1994-02-01

申请人： Oh-Kyong Kwon ,  Taylor R. Efland ,  Satwinder Malhi ,  Wai T. Ng

发明人： Oh-Kyong Kwon ,  Taylor R. Efland ,  Satwinder Malhi ,  Wai T. Ng

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L27/092 ,  H01L27/105

CPC分类号： H01L29/66681 ,  H01L29/7801 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  Y10S148/096

摘要： A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12). A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).

摘要翻译： 晶体管（10）在第一导电类型的半导体衬底（12）上具有第二导电类型的薄外延层（14）。 形成第二导电类型的漂移区（24），延伸穿过薄外延层（14）到衬底（12）。 在漂移区（24）上形成厚的绝缘体层（26）。 第一导电类型的IGFET体（28）形成在漂移区（24）附近。 第二导电类型的源极区域（34）形成在IGFET主体（28）内并且与漂移区域（24）间隔开，从而限定IGFET体（28）内的沟道区域（40）。 导电栅极（32）被绝缘地设置在IGFET主体（28）上并且从源极区域（34）延伸到厚的绝缘体层（26）。 在漂移区（24）附近形成漏区（36）。

公开(公告)号：US5346835A

公开(公告)日：1994-09-13

申请号：US95805

申请日：1993-07-21

申请人： Satwinder Malhi ,  Taylor R. Efland ,  Oh-Kyong Kwon

发明人： Satwinder Malhi ,  Taylor R. Efland ,  Oh-Kyong Kwon

IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/266

CPC分类号： H01L29/0847 ,  H01L27/088 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/0615 ,  H01L29/42368 ,  Y10S148/126

摘要： A triple-diffused lateral RESURF transistor (55,57) uses a threshold voltage adjust implant (52, 54) in conjunction with a thinner gate oxide (64) to yield a device which is more compatible with CMOS VLSI manufacturing processes and which delivers better performance characteristics than more conventional double-diffused RESURF transistor devices.

摘要翻译： 三扩散横向RESURF晶体管（55,57）使用阈值电压调整注入（52,54）与更薄的栅极氧化物（64）结合，以产生与CMOS VLSI制造工艺更兼容并且更好地传输的器件 性能特征比更传统的双扩散RESURF晶体管器件。

公开(公告)号：US5578514A

公开(公告)日：1996-11-26

申请号：US241543

申请日：1994-05-12

申请人： Oh-Kyong Kwon ,  Taylor R. Efland ,  Satwinder Malhi ,  Wai T. Ng

发明人： Oh-Kyong Kwon ,  Taylor R. Efland ,  Satwinder Malhi ,  Wai T. Ng

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66681 ,  H01L29/7801 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  Y10S148/096

摘要： A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12). A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).

摘要翻译： 晶体管（10）在第一导电类型的半导体衬底（12）上具有第二导电类型的薄外延层（14）。 形成第二导电类型的漂移区（24），延伸穿过薄外延层（14）到衬底（12）。 在漂移区（24）上形成厚的绝缘体层（26）。 第一导电类型的IGFET体（28）形成在漂移区（24）附近。 第二导电类型的源极区域（34）形成在IGFET主体（28）内并且与漂移区域（24）间隔开，从而限定IGFET体（28）内的沟道区域（40）。 导电栅极（32）被绝缘地设置在IGFET主体（28）上并且从源极区域（34）延伸到厚的绝缘体层（26）。 在漂移区（24）附近形成漏区（36）。

公开(公告)号：US5070297A

公开(公告)日：1991-12-03

申请号：US532481

申请日：1990-06-04

申请人： Oh-Kyong Kwon ,  Masashi Hashimoto ,  Satwinder Malhi ,  Eng C. Born

发明人： Oh-Kyong Kwon ,  Masashi Hashimoto ,  Satwinder Malhi ,  Eng C. Born

IPC分类号： G01R31/317 ,  G01R31/319 ,  G01R31/3193

CPC分类号： G01R31/31713 ,  G01R31/31905 ,  G01R1/07314 ,  G01R31/31935

摘要： A full wafer integrated circuit testing device (10) tests integrated circuits (15) formed as a wafer in conjunction with a test control unit (40). Probe units (14) associate with respective integrated circuits (15). Probe tips (16) on probe units (14) communicate with respective pads (19) with the integrated circuits (15). Interface circuitry (36) selectively communicates test data between the test control unit (40) and the integrated circuit (15). Test pins (16) have positions on probe units (14) associated with respective integrated circuit connection points (19) for testing associated integrated circuit (15) components. Interface circuitry (36) includes comparators (54 and 56) that compare signals between the integrated circuit (15) and the test control unit (40). Memory components (66 and 68) store data associated with signals from test control unit (40) and said integrated circuit (15). Compliant material (32) assures that probe tips (16) throughout probe card (10) positively and conductively engage integrated circuit pads (19) of all associated integrated circuits (15) of a wafer.

摘要翻译： 整个晶片集成电路测试装置（10）测试与测试控制单元（40）一起形成为晶片的集成电路（15）。 探头单元（14）与相应的集成电路（15）相关联。 探针单元（14）上的探针尖端（16）与具有集成电路（15）的各个焊盘（19）连通。 接口电路（36）选择性地在测试控制单元（40）和集成电路（15）之间通信测试数据。 测试引脚（16）在与相应的集成电路连接点（19）相关联的探针单元（14）上具有位置，用于测试相关联的集成电路（15）组件。 接口电路（36）包括比较器（54和56），其比较集成电路（15）和测试控制单元（40）之间的信号。 存储器组件（66和68）存储与来自测试控制单元（40）和所述集成电路（15）的信号相关联的数据。 符合标准的材料（32）确保探针卡（10）中的探针尖端（16）积极地和导电地接合晶片的所有相关联的集成电路（15）的集成电路板（19）。

公开(公告)号：US5457068A

公开(公告)日：1995-10-10

申请号：US985095

申请日：1992-11-30

申请人： Satwinder Malhi ,  Chi-Cheong Shen ,  Oh-Kyong Kwon

发明人： Satwinder Malhi ,  Chi-Cheong Shen ,  Oh-Kyong Kwon

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L23/36 ,  H01L23/532 ,  H01L23/66 ,  H01P11/00 ,  H01L21/44

CPC分类号： H01L21/768 ,  H01L21/76297 ,  H01L23/36 ,  H01L23/53271 ,  H01L23/66 ,  H01L2924/0002

摘要： A monolithic integrated circuit capable of operation in the microwave range which is fabricated using silicon technology wherein transmission line interconnects are fabricated along with active devices on the same substrate. The transmission line is provided using polycrystalline silicon since it can have much higher resistivity than single crystal silicon. Accordingly, a circuit is provided wherein active devices are provided in single crystal silicon and interconnects are formed overlying polycrystalline silicon to provide transmission line interconnects between devices and obtain the desired high frequency response. This is accomplished by providing a highly doped silicon substrate of predetermined conductivity type having a less highly doped silicon layer thereon of the same conductivity type with an oxide layer over the less highly doped layer, forming mesas for formation therein of active elements in the structure having valleys between the mesas extending into the substrate, filling the valleys with very high resistivity polysilicon, forming an electrically insulating layer over the polysilicon, forming active elements with contacts thereto in the mesas and forming interconnects between contacts of the active elements extending over the high resistivity polysilicon regions and the electrically insulating material thereover.

摘要翻译： 能够在微波范围内操作的单片集成电路，其使用硅技术制造，其中传输线互连与有源器件一起制造在同一衬底上。 传输线使用多晶硅提供，因为它可以具有比单晶硅高得多的电阻率。 因此，提供了一种电路，其中在单晶硅中提供有源器件，并且在多晶硅上形成互连以在器件之间提供传输线互连并获得期望的高频响应。 这是通过提供具有相同导电类型的具有相同导电类型的较低掺杂硅层的高掺杂硅衬底，在较高掺杂层上形成氧化物层，形成台面以在其中形成结构中的有源元件，其中具有 位于延伸到衬底中的台面之间的谷部，用非常高电阻率的多晶硅填充谷，在多晶硅上形成电绝缘层，在台面中形成与其接触的有源元件，并形成在高电阻率上延伸的有源元件的触点之间的互连 多晶硅区域和其上的电绝缘材料。

公开(公告)号：US5088190A

公开(公告)日：1992-02-18

申请号：US575456

申请日：1990-08-30

申请人： Satwinder Malhi ,  Oh-Kyong Kwon

发明人： Satwinder Malhi ,  Oh-Kyong Kwon

IPC分类号： G01R1/04 ,  G01R31/28

CPC分类号： G01R31/2863 ,  G01R1/0483 ,  G01R31/2886 ,  H01R12/57 ,  H01L2224/48091 ,  H01L2924/01014 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01R12/714 ,  Y10T29/49149

摘要： An integrated circuit AC test and burn-in socket (10) for communicating test signals between test circuitry and an integrated circuit chip (11) comprises connection circuitry (32) associated to engage the chip (11) and communicate test signals between the chip (11) and the test circuitry. A compliant base (34) supports the circuitry (32) and assures positive engagement and electrical connection between the circuitry (32) and the chip (11). A socket assembly (20 and 21) holds the chip (11) in engagement with the connection circuitry (32).

摘要翻译： 用于在测试电路和集成电路芯片（11）之间传送测试信号的集成电路AC测试和老化插座（10）包括与芯片（11）相关联的连接电路（32），并在芯片（11）之间传送测试信号 11）和测试电路。 柔性基座（34）支撑电路（32）并且确保电路（32）和芯片（11）之间的正接合和电连接。 插座组件（20和21）将芯片（11）保持与连接电路（32）接合。

公开(公告)号：US5059897A

公开(公告)日：1991-10-22

申请号：US447328

申请日：1989-12-07

申请人： Thomas J. Aton ,  Satwinder Malhi ,  Masashi Hashimoto ,  Shivaling S. Mahant-Shitti ,  Oh-Kyong Kwon ,  Thirumalai Sridhar

发明人： Thomas J. Aton ,  Satwinder Malhi ,  Masashi Hashimoto ,  Shivaling S. Mahant-Shitti ,  Oh-Kyong Kwon ,  Thirumalai Sridhar

IPC分类号： G01R31/28 ,  H01L21/66

CPC分类号： G01R31/281

摘要： A system and method for testing the continuity of interconnecting nets on a substrate to be used in multi-chip technology is provided. The system includes coupling a test pad (15) to the net (12) to be tested. The test pad (15) is coupled through a diode (34) to a common node (32). The voltage of a first node (16) of the net (12) is sensed by a voltmeter (38) which is coupled to ground. A predetermined current signal is applied to each node (16, 18, 20, 22) in the net through the use of a probe (42). The voltage of the remaining nets (14) is sensed by a voltmeter (44). If an erroneous interconnection (31) is present between the net (12) to be tested and any other net (14) on the substrate, the voltage of the other net (14) will fluctuate. The voltmeter (38) will indicate if there is an electrical connection between the node (16) and the test pad (15) during testing. If an electrical path is established between each node in the net (12) and test pad (15), the continuity of the net (12) is established through the operation of Ohm's law.

摘要翻译： 提供了一种用于测试在多芯片技术中使用的基板上互连网络的连续性的系统和方法。 该系统包括将测试垫（15）耦合到要测试的网（12）。 测试焊盘（15）通过二极管（34）耦合到公共节点（32）。 网（12）的第一节点（16）的电压由耦合到地的电压计（38）感测。 通过使用探针（42）将预定电流信号施加到网中的每个节点（16,18,20,22）。 剩余网（14）的电压由电压计（44）感测。 如果要测试的网络（12）和基板上的任何其他网络（14）之间存在错误的互连（31），则另一个网络（14）的电压将波动。 电压表（38）将指示在测试期间节点（16）和测试垫（15）之间是否存在电气连接。 如果在网络（12）和测试板（15）中的每个节点之间建立电路径，则通过欧姆定律的操作建立网络（12）的连续性。