公开(公告)号：US20130234228A1

公开(公告)日：2013-09-12

申请号：US13572731

申请日：2012-08-13

申请人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

发明人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC分类号： H01L27/115

CPC分类号： H01L27/11558 ,  G11C16/0433 ,  G11C2216/10 ,  H01L29/42328 ,  H01L29/7883 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮栅晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。 栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同 栅氧化层。

公开(公告)号：US08592886B2

公开(公告)日：2013-11-26

申请号：US13572731

申请日：2012-08-13

申请人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

发明人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC分类号： H01L29/788 ,  H01L29/06

CPC分类号： H01L27/11558 ,  G11C16/0433 ,  G11C2216/10 ,  H01L29/42328 ,  H01L29/7883 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮动栅极晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。 栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同 栅氧化层。

公开(公告)号：US08658495B2

公开(公告)日：2014-02-25

申请号：US13602404

申请日：2012-09-04

申请人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Wen-Hao Ching ,  Wei-Ren Chen

发明人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC分类号： H01L29/788

CPC分类号： H01L21/28 ,  H01L27/11558 ,  H01L27/1156 ,  H01L29/401

摘要： The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.

摘要翻译： 本发明提供一种制造可擦除可编程单多晶非易失性存储器的方法，包括以下步骤：在第一类型衬底中限定第一区域和第二区域; 在所述第一区域中形成第二类型井区域; 形成覆盖所述第一区域的表面的第一栅极氧化物层和第二栅极氧化物层，其中所述第二栅极氧化物层延伸到所述第二区域并邻近所述第二区域; 在第二区域中形成DDD区域; 在所述第二区域上方蚀刻所述第二栅极氧化物层的一部分; 形成覆盖所述第一和第二栅极氧化物层的两个多晶硅栅极; 以及限定所述DDD区域中的第二类型掺杂区域并限定所述第二类型阱区域中的第一类型掺杂区域。

公开(公告)号：US20130237048A1

公开(公告)日：2013-09-12

申请号：US13602404

申请日：2012-09-04

申请人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Wen-Hao Ching ,  Wei-Ren Chen

发明人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC分类号： H01L21/28

CPC分类号： H01L21/28 ,  H01L27/11558 ,  H01L27/1156 ,  H01L29/401

摘要： The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region.

公开(公告)号：US08787092B2

公开(公告)日：2014-07-22

申请号：US13418352

申请日：2012-03-13

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Hsin-Ming Chen

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Hsin-Ming Chen

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0433

摘要： The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage.

摘要翻译： 本发明提供一种非易失性存储装置。 非易失性存储装置包括多个存储单元和信号发生器。 存储单元被布置成阵列，并且每个存储单元具有控制栅极端子，浮动栅极，源极线端子，位线端子，所选择的栅极端子和字线端子。 信号发生器耦合到存储单元。 当非易失性存储器件执行编程操作时，信号发生器向存储器单元中的多个禁止的存储单元的控制栅极端提供编程信号。 其中编程信号是具有直流（DC）偏移电压的脉冲信号。

公开(公告)号：US20130234227A1

公开(公告)日：2013-09-12

申请号：US13415185

申请日：2012-03-08

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L27/115

CPC分类号： H01L29/42328 ,  G11C16/0408 ,  H01L27/11558 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括包括选择栅极，第一p型掺杂区域和第二p型掺杂区域的第一PMOS晶体管，其中选择栅极连接到选择栅极电压，并且第一 p型掺杂区域连接到源极线电压; 包括第二p型掺杂区的第二PMOS晶体管，第三p型掺杂区和浮置栅，其中第三p型掺杂区连接到位线电压; 以及与浮置栅极相邻的擦除栅极区域，其中擦除栅极区域连接到擦除线电压。

公开(公告)号：US08941167B2

公开(公告)日：2015-01-27

申请号：US13415185

申请日：2012-03-08

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L29/788

CPC分类号： H01L29/42328 ,  G11C16/0408 ,  H01L27/11558 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括包括选择栅极，第一p型掺杂区域和第二p型掺杂区域的第一PMOS晶体管，其中选择栅极连接到选择栅极电压，并且第一 p型掺杂区域连接到源极线电压; 包括第二p型掺杂区的第二PMOS晶体管，第三p型掺杂区和浮置栅，其中第三p型掺杂区连接到位线电压; 以及与浮置栅极相邻的擦除栅极区域，其中擦除栅极区域连接到擦除线电压。

公开(公告)号：US20130242663A1

公开(公告)日：2013-09-19

申请号：US13418352

申请日：2012-03-13

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Hsin-Ming Chen

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Hsin-Ming Chen

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0433

摘要： The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage.

摘要翻译： 本发明提供一种非易失性存储装置。 非易失性存储装置包括多个存储单元和信号发生器。 存储单元被布置成阵列，并且每个存储单元具有控制栅极端子，浮动栅极，源极线端子，位线端子，所选择的栅极端子和字线端子。 信号发生器耦合到存储单元。 当非易失性存储器件执行编程操作时，信号发生器向存储器单元中的多个禁止的存储单元的控制栅极端提供编程信号。 其中编程信号是具有直流（DC）偏移电压的脉冲信号。

公开(公告)号：US08456916B2

公开(公告)日：2013-06-04

申请号：US13541755

申请日：2012-07-04

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.

摘要翻译： 唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。 第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

公开(公告)号：US08705289B2

公开(公告)日：2014-04-22

申请号：US13344621

申请日：2012-01-06

申请人： Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ming Ku ,  Yung-Hsiang Chen ,  Shih-Chen Wang ,  Hsin-Ming Chen

发明人： Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ming Ku ,  Yung-Hsiang Chen ,  Shih-Chen Wang ,  Hsin-Ming Chen

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C16/12

摘要： A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.

摘要翻译： 提供一种闪存装置。 闪存装置包括多个存储单元和多个编程电压控制发生器。 每个存储单元通过其控制端接收编程控制电压，并根据编程控制电压执行数据编程操作。 每个编程电压控制发生器包括预充电电压发射器和泵浦电容器。 预充电电压发射器在第一时段期间根据预充电使能信号向每个相应存储器单元的末端提供预充电电压。 在第二时段期间向泵浦电容器提供泵浦电压，并且在每个存储器单元的控制端产生编程控制电压。