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公开(公告)号：US09093445B2
公开(公告)日：2015-07-28
申请号：US13219084
申请日：2011-08-26
IPC分类号： H03K3/00 , H01L23/50 , H01L25/065 , G11C11/4072
CPC分类号： H01L23/50 , G11C11/4072 , H01L25/0657 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/0002 , H03K3/00 , H01L2924/00
摘要： Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.
摘要翻译： 提供了用于在堆叠结构中包装相同处理的芯片的方法和结构。 闩锁链包括与第一芯片相关联的具有单个或多个闩锁的第一闩锁链。 第一锁存链被构造成从第一芯片读取数据信息。 闩锁链包括具有与第二芯片相关联的单个或多个闩锁的第二闩锁链。 第二锁存链被构造成从第二芯片读取数据信息。 第一锁存链和第二锁存链彼此连接，使得形成跨越码片边界的单个锁存链。 第一锁存链和第二锁存链被构造成分别提供用于识别第一芯片和第二芯片的识别信息。
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公开(公告)号：US20140033148A1
公开(公告)日：2014-01-30
申请号：US13557386
申请日：2012-07-25
申请人： Erwin B. Cohen , Mark C.H. Lamorey , Marek A. Orlowski , Douglas O. Powell , David L. Questad , David B. Stone , Paul R. Walling
发明人： Erwin B. Cohen , Mark C.H. Lamorey , Marek A. Orlowski , Douglas O. Powell , David L. Questad , David B. Stone , Paul R. Walling
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.
摘要翻译： 计算机实现的方法提供了倒装芯片封装的芯片载体的弹性模量图。 将包括芯片载体的每个层的每个垂直对准子区域的电介质和导电设计元件的设计数据建模为弹簧以提供弹性模量图。 确定芯片载体的子区域的弹性模量在芯片接合期间识别可能的机械故障位置并冷却倒装芯片封装。 将焊料凸块修改为芯片载体可以减少施加到识别的可能的机械故障位置的应力。 修改芯片载体设计以减少与识别出的可能的机械故障位置相关联的子区域的刚度，还可减少芯片连接和冷却的应力。
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3.发明申请STRUCTURE AND METHOD FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS 有权用于监测焊接电路集成电路交互介质层应力诱发失效的结构与方法公开(公告)号：US20130292817A1
公开(公告)日：2013-11-07
申请号：US13461912
申请日：2012-05-02
CPC分类号： H01L22/34 , H01L23/49816 , H01L23/50 , H01L23/5283 , H01L23/5329 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05008 , H01L2224/05073 , H01L2224/05124 , H01L2224/0554 , H01L2224/05572 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/14515 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/15311 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.
摘要翻译： 一种用于监测层间介电应力损伤的结构和方法。 该结构包括一个监测焊锡凸块和一般焊锡凸块; 在衬底和监测焊料凸点之间的一组层叠的层间电介质层和正常的焊料凸点，一个或多个包含介电常数为2.4或更小的超低K材料的超低K电介质层; 在超低K电介质层中的监视器焊料凸块正下方的区域中的监视器结构，并且其中在监视器焊料凸块正下方的区域中的至少一个超低K电介质层中的导体密度小于规定的最小值 正常焊锡凸块下的超低K电介质层的相应区域的密度和导体密度大于规定的最小密度。
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公开(公告)号：US20130285251A1
公开(公告)日：2013-10-31
申请号：US13459785
申请日：2012-04-30
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/768 , H01L23/5226 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
摘要翻译： 集成电路结构包括形成层叠结构的多个绝缘体层（彼此连接）。 进一步包括在每个绝缘体层内的开口，以及通孔开口内的导电通孔材料。 相邻绝缘体层的对应的通孔内的导电通孔材料电连接以形成通过层压结构的顶表面和底表面之间的绝缘体层的连续的电通路。 在每个连续的电通路中，通孔相对于彼此定位，以形成通过层压结构的导电过孔材料的对角线结构路径。 相邻绝缘体层的相应通孔开始部分重叠。 对角结构路径与顶面和底面非垂直。
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5.发明申请公开(公告)号：US20130270558A1
公开(公告)日：2013-10-17
申请号：US13448775
申请日：2012-04-17
申请人： James V. Crain, JR. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
发明人： James V. Crain, JR. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
IPC分类号： H01L23/498 , H01L21/66
CPC分类号： H01L22/34 , G01R31/2601 , G01R31/2607 , H01L23/522 , H01L24/13 , H01L24/14 , H01L2224/13111 , H01L2224/14131 , H01L2224/14515 , H01L2924/01029 , H01L2924/01047 , H01L2924/01051 , H01L2924/01082 , H01L2924/01083 , H01L2924/14
摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.
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公开(公告)号：US20130049834A1
公开(公告)日：2013-02-28
申请号：US13219084
申请日：2011-08-26
IPC分类号： H03K3/00
CPC分类号： H01L23/50 , G11C11/4072 , H01L25/0657 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/0002 , H03K3/00 , H01L2924/00
摘要： Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.
摘要翻译： 提供了用于在堆叠结构中包装相同处理的芯片的方法和结构。 闩锁链包括与第一芯片相关联的具有单个或多个闩锁的第一闩锁链。 第一锁存链被构造成从第一芯片读取数据信息。 闩锁链包括具有与第二芯片相关联的单个或多个闩锁的第二闩锁链。 第二锁存链被构造成从第二芯片读取数据信息。 第一锁存链和第二锁存链彼此连接，使得形成跨越码片边界的单个锁存链。 第一锁存链和第二锁存链被构造成分别提供用于识别第一芯片和第二芯片的识别信息。
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7.发明申请ELECTRICAL PROPERTY ALTERING, PLANAR MEMBER WITH SOLDER ELEMENT IN IC CHIP PACKAGE 有权电气设备改造，带有芯片包装中的焊接元件的平面构件公开(公告)号：US20100327405A1
公开(公告)日：2010-12-30
申请号：US12491438
申请日：2009-06-25
申请人： J. Richard Behun , David B. Stone
发明人： J. Richard Behun , David B. Stone
CPC分类号： H01L23/50 , H01L23/49811 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/16 , H01L2224/0401 , H01L2224/05599 , H01L2224/131 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00
摘要： A structure includes a solder element for electrically coupling a substrate of an integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member positioned between the solder element and at least one of a landing pad of the substrate and a landing pad of the PCB. In another embodiment, the electrical property altering, planar member can be applied to the solder element(s) between the IC chip and the package substrate.
摘要翻译： 一种结构包括用于电耦合集成电路（IC）芯片封装的衬底和印刷电路板（PCB）的焊料元件; 以及位于所述焊料元件与所述基板的着陆焊盘和所述PCB的着陆焊盘中的至少一个之间的第一电性质改变的基本平坦的构件。 在另一个实施例中，电性能改变的平面构件可以被施加到IC芯片和封装衬底之间的焊料元件。
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公开(公告)号：US20100281610A1
公开(公告)日：2010-11-11
申请号：US12463507
申请日：2009-05-11
申请人： David B. Stone
发明人： David B. Stone
IPC分类号： E04H4/10
CPC分类号： E04H4/101
摘要： A pool cover, pool covering apparatus, system and method for covering a pool: A swimming pool cover consisting of two layers, suitably bonded together, with air trapped in gas tight compartments extending across the width of the cover. These features give the cover improved lateral stiffness, low wetted surface area, and a feedback mechanism for centering the cover as it is being rolled up. A pool covering apparatus that consists of: A movable reel assembly that can also be used a seat to store the cover wrapped around a shaft; A float, attached to the cover, to pull the cover onto the pool when the operator by means of a rope pulls it onto the pool; A cranking device to wind up the cover on the shaft in the reel assembly to remove the cover from the pool. The pool is broken down into a plurality of sections, one apparatus serving each section, to allow an easily operated system to cover a large pool and to allow the design features of the cover make it easier to deploy and remove.
摘要翻译： 游泳池盖，游泳池覆盖设备，系统和方法，用于覆盖游泳池：由两层组成的游泳池盖，适当地粘合在一起，空气被封闭在覆盖盖的宽度上的气密隔间中。 这些特征使得盖子改善了侧向刚度，低润湿表面积，以及用于在覆盖物卷起时使盖对中的反馈机构。 一种游泳池覆盖设备，包括：可移动的卷轴组件，其也可以用于座椅，用于存放缠绕在轴上的盖子; 当操作者通过绳索将其拉到池上时，附着在盖上的浮子将盖子拉到池上; 一个启动装置，用于将卷轴组件中的轴上的盖子卷起，以从池中移除盖子。 池被分解为多个部分，一个设备用于每个部分，以允许容易操作的系统覆盖大型池并且允许盖的设计特征使得更容易部署和移除。
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公开(公告)号：US07348792B2
公开(公告)日：2008-03-25
申请号：US11491216
申请日：2006-07-21
申请人： Jason E. Blanchet , James V. Crain, Jr. , Charles W. Griffin , David B. Stone , Robert F. White
发明人： Jason E. Blanchet , James V. Crain, Jr. , Charles W. Griffin , David B. Stone , Robert F. White
CPC分类号： G01R31/2856 , G01R31/2853 , G01R31/2855 , G01R31/2875 , G01R31/2879
摘要： A test chip module for testing the integrity of the flip chip solder ball interconnections between chip and substrate. The interconnections are thermally stressed through an array of individual heaters formed in a layer of chip metallurgy to provide a uniform and ubiquitous source of heat. Current is passed through the interconnection to be tested by a current supply circuit using one signal I/O interconnection and the voltage drop across the interconnection to be tested from the current passed therethrough is measured by a voltage measuring circuit connected through another signal I/O interconnection. Stress initiating cracking and degradation at the interconnection creates a measurable change in voltage drop across the interconnection.
摘要翻译： 用于测试芯片和衬底之间的倒装芯片焊球互连的完整性的测试芯片模块。 互连通过在芯片冶金层中形成的各个加热器的阵列进行热应力，以提供均匀且普遍存在的热源。 电流通过互连使用一个信号I / O互连由电流供应电路进行测试，并且通过其中通过的电流将要测试的互连线上的电压降由通过另一个信号I / O连接的电压测量电路测量 互连。 在互连处的应力引发开裂和退化在互连上产生可测量的电压降变化。
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10.发明授权公开(公告)号：US07160972B2
公开(公告)日：2007-01-09
申请号：US10779177
申请日：2004-02-12
申请人： Nickelous David Young , David B. Stone, legal representative , Robert Vincent Thomaier , Keith Bryan Reichel
IPC分类号： C08G77/12
摘要： A thermally stable polysiloxane composition is a cross-linked product of a Part A composition, of a Part B composition and a catalyst, the Part A composition being a polysiloxane having 60 to 75 percent by weight phenyl groups, the Part B composition being a polysiloxane having 50 to 80 percent by weight phenyl groups. The composition has the properties of optical clarity as measured by 90% or greater transmission of light of 400 nm wavelength in a 1.0 centimeter path, a refractive index at 589 nm of 1.545 or greater and still has 90% or greater transmission of light of 400 nm wavelength in a 1.0 centimeter path after exposure to 150° C. for 6 hours. The composition is well suited for application as an optically transmissive cover or lens for light emitting diodes and for use in other optical and related devices.
摘要翻译： 热稳定的聚硅氧烷组合物是部分A组合物，部分B组合物和催化剂的交联产物，部分A组合物是具有60至75重量％苯基的聚硅氧烷，部分B组合物是聚硅氧烷 具有50至80重量％的苯基。 该组合物具有通过在1.0厘米路径中的波长为400nm的光的90％或更高透射率测量的光学透明度的性质，589nm的折射率为1.545或更大，并且仍具有90％或更高的透光率为400 nm波长在暴露于150℃6小时后的1.0厘米路径中。 该组合物非常适合用作发光二极管的光学透射盖或透镜并用于其它光学和相关装置。
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