公开(公告)号：US07492011B2

公开(公告)日：2009-02-17

申请号：US11273400

申请日：2005-11-15

申请人： Teruo Suzuki ,  Kenji Hashimoto ,  Toshio Nomura

发明人： Teruo Suzuki ,  Kenji Hashimoto ,  Toshio Nomura

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： To present a semiconductor device mounting ESD protective device appropriately applicable to transistors mutually different in dielectric strength, and its manufacturing method. The semiconductor device comprises a first ESD protective circuit 1A including a first transistor 3 and a first ballast resistance 4, and a second ESD protective circuit 1B including a second transistor 5 and a second ballast resistance 6. The impurity concentration of the second diffusion region forming the first ballast resistance 4 is set lower than the impurity concentration of the fourth diffusion region for forming the second ballast resistance 6.

摘要翻译： 提出一种适用于介电强度相互不同的晶体管的半导体器件的ESD保护器及其制造方法。 该半导体器件包括包括第一晶体管3和第一镇流电阻4的第一ESD保护电路1A和包括第二晶体管5和第二镇流电阻6的第二ESD保护电路1B。第二扩散区域形成的杂质浓度 第一镇流电阻4被设定为低于用于形成第二镇流电阻6的第四扩散区的杂质浓度。

公开(公告)号：US20060273398A1

公开(公告)日：2006-12-07

申请号：US11273400

申请日：2005-11-15

申请人： Teruo Suzuki ,  Kenji Hashimoto ,  Toshio Nomura

发明人： Teruo Suzuki ,  Kenji Hashimoto ,  Toshio Nomura

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： To present a semiconductor device mounting ESD protective device appropriately applicable to transistors mutually different in dielectric strength, and its manufacturing method. The semiconductor device comprises a first ESD protective circuit 1A including a first transistor 3 and a first ballast resistance 4, and a second ESD protective circuit 1B including a second transistor 5 and a second ballast resistance 6. The impurity concentration of the second diffusion region forming the first ballast resistance 4 is set lower than the impurity concentration of the fourth diffusion region for forming the second ballast resistance 6.

摘要翻译： 提出一种适用于介电强度相互不同的晶体管的半导体器件的ESD保护器及其制造方法。 半导体器件包括包括第一晶体管3和第一镇流电阻4的第一ESD保护电路1A和包括第二晶体管5和第二镇流电阻6的第二ESD保护电路1B。 形成第一镇流电阻4的第二扩散区域的杂质浓度设定为低于用于形成第二镇流电阻6的第四扩散区域的杂质浓度。

公开(公告)号：US20060001097A1

公开(公告)日：2006-01-05

申请号：US10995513

申请日：2004-11-24

申请人： Toshio Nomura ,  Kenji Hashimoto ,  Teruo Suzuki

发明人： Toshio Nomura ,  Kenji Hashimoto ,  Teruo Suzuki

IPC分类号： H01L21/331 ,  H01L23/62

CPC分类号： H01L21/823418 ,  H01L27/0266

摘要： A protection transistor which protects an internal transistor in an internal circuit from breakage due to static electricity occurring between power supply pads is provided. A conductivity type of a first p-well constructing a channel of the protection transistor corresponds to a conductivity type of a second p-well constructing a channel of the internal transistor. An impurity concentration of the first p-well is higher than an impurity concentration of the second p-well. Accordingly, drain junction of the protection transistor is sharper than drain junction of the internal transistor, and starting voltage of a parasitic bipolar operation of the protection transistor is lower than that of the internal transistor. Therefore, the internal circuit can be properly protected from an ESD surge.

摘要翻译： 提供保护内部电路中的内部晶体管免受因电源焊盘之间的静电而损坏的保护晶体管。 构成保护晶体管的沟道的第一p阱的导电类型对应于构成内部晶体管的沟道的第二p阱的导电类型。 第一p阱的杂质浓度高于第二p阱的杂质浓度。 因此，保护​​晶体管的漏极结比内部晶体管的漏极结更尖锐，并且保护晶体管的寄生双极性工作的启动电压低于内部晶体管的启动电压。 因此，可以正确保护内部电路免受ESD浪涌。

公开(公告)号：US06897536B2

公开(公告)日：2005-05-24

申请号：US10441216

申请日：2003-05-20

申请人： Toshio Nomura ,  Teruo Suzuki

发明人： Toshio Nomura ,  Teruo Suzuki

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0277

摘要： An ESD-protection device includes a gate electrode formed on a substrate; a first diffusion region of a first conductivity type formed in the substrate at a first side of the gate electrode, a second diffusion region of the first conductivity type formed in the substrate at a second side of the gate electrode, and a third diffusion region of a second conductivity type formed in the substrate underneath the second diffusion region in contact with the second diffusion region. Thereby, the impurity concentration level of the third diffusion region is set to be larger than the impurity concentration level of the region of the substrate located at the same depth right underneath the gate electrode.

摘要翻译： ESD保护器件包括形成在衬底上的栅电极; 第一导电类型的第一扩散区域形成在栅电极的第一侧的衬底中，在栅电极的第二侧形成在衬底中的第一导电类型的第二扩散区，以及第三扩散区 形成在与第二扩散区域接触的第二扩散区域下方的衬底中的第二导电类型。 因此，第三扩散区域的杂质浓度水平被设定为大于位于栅电极下方相同深度的基板的区域的杂质浓度水平。

公开(公告)号：US20060232318A1

公开(公告)日：2006-10-19

申请号：US11216004

申请日：2005-09-01

申请人： Junji Iwahori ,  Teruo Suzuki ,  Kenji Hashimoto ,  Noriaki Saito

发明人： Junji Iwahori ,  Teruo Suzuki ,  Kenji Hashimoto ,  Noriaki Saito

IPC分类号： H03K5/08

CPC分类号： H02H9/046 ,  H01L27/0285 ,  H03K5/08

摘要： A power clamp circuit for preventing unnecessary power supply leak current at a tolerable power supply noise level. A reference voltage circuit generates a reference voltage by reducing a positive voltage supplied from a first power supply terminal by a predetermined potential and supplies the reference voltage to a buffer circuit. The buffer circuit activates a transistor functioning as a clamp element based on the reference voltage to short-circuit the first and second power supply terminals.

摘要翻译： 一种用于在可容忍的电源噪声水平下防止不必要的电源泄漏电流的功率钳位电路。 参考电压电路通过将从第一电源端子提供的正电压减小预定电位来产生参考电压，并将参考电压提供给缓冲电路。 缓冲电路基于参考电压激活用作钳位元件的晶体管，以使第一和第二电源端子短路。

公开(公告)号：US08354723B2

公开(公告)日：2013-01-15

申请号：US12034173

申请日：2008-02-20

申请人： Teruo Suzuki

发明人： Teruo Suzuki

IPC分类号： H01L27/06 ,  H01L21/336

CPC分类号： H01L21/04 ,  H01L21/823425 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/7833

摘要： An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first suicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.

摘要翻译： 一种静电放电保护装置，包括形成在基板上的栅电极。 第一导电类型的第一和第二扩散区域形成在基板中，栅电极位于其间。 在第一扩散区域中形成第一硅化物层。 在栅电极和第一硅化物层之间形成硅化物块区域。 在第一硅化物层的下方形成第三扩散区，以与第一扩散区部分重叠。 第三扩散区和第一硅化物层具有基本相同的形状和尺寸。 第三扩散区域和位于与第三扩散区域相同深度的栅电极下方的部分包含第二导电类型的杂质。 第三扩散区域的杂质浓度高于栅电极下方的杂质浓度。

公开(公告)号：US20110234298A1

公开(公告)日：2011-09-29

申请号：US13049072

申请日：2011-03-16

申请人： Teruo Suzuki

发明人： Teruo Suzuki

IPC分类号： H03K17/687

CPC分类号： G05F3/24

摘要： Provided is a reference voltage circuit having a soft start function, which is small in circuit size and is capable of providing a continuous voltage. The reference voltage circuit includes a reference voltage section and a soft start circuit. The reference voltage section includes a depletion mode MOS transistor and a first enhancement mode MOS transistor. The soft start circuit includes: a second enhancement mode MOS transistor having a gate connected to a gate and a drain of the first enhancement mode MOS transistor, and a drain connected to an output terminal of the reference voltage circuit; a MOS switch having one terminal connected to an output terminal of the reference voltage section, and another terminal connected to the drain of the second enhancement mode MOS transistor; and a constant current source and a capacitor connected in series between a power supply and a ground.

摘要翻译： 提供了具有软启动功能的参考电压电路，其电路尺寸小并且能够提供连续电压。 参考电压电路包括参考电压部分和软启动电路。 参考电压部分包括耗尽型MOS晶体管和第一增强型MOS晶体管。 软起动电路包括：第二增强型MOS晶体管，其具有连接到第一增强型MOS晶体管的栅极和漏极的栅极，以及连接到参考电压电路的输出端子的漏极; 一个MOS开关，其一个端子连接到参考电压部分的输出端子，另一个端子连接到第二增强模式MOS晶体管的漏极; 以及在电源和地之间串联连接的恒流源和电容器。

公开(公告)号：US20090189584A1

公开(公告)日：2009-07-30

申请号：US12357762

申请日：2009-01-22

申请人： Teruo Suzuki

发明人： Teruo Suzuki

IPC分类号： G05F1/10

CPC分类号： G05F1/573

摘要： Provided is a voltage regulator capable of reducing fluctuation of an output current even when an output terminal thereof is short-circuited. In a case where the output terminal of the voltage regulator is short-circuited, an output current (Iout) of the voltage regulator is limited and fixed to a limit current value. When an output voltage (Vout) of the voltage regulator decreases to have a value equal to or smaller than not a detection voltage value (Vref3) of a reference voltage circuit (34) but a detection voltage value (Vref2) of a reference voltage circuit (31), a second limit operation in which the output voltage (Iout) is further limited to be decreased is set. Further, in a case where the output terminal is short-circuited and then reset, when the output voltage (Vout) has a value equal to or larger than not the detection voltage value (Vref2) but the detection voltage value (Vref3), the second limit operation is canceled.

摘要翻译： 提供一种即使当其输出端子短路时也能够减小输出电流的波动的电压调节器。 在电压调节器的输出端子短路的情况下，电压调节器的输出电流（Iout）被限制并固定为极限电流值。 当电压调节器的输出电压（Vout）减小到等于或小于参考电压电路（34）的检测电压值（Vref3）或参考电压电路（34）的检测电压值（Vref2） （31），设定输出电压（Iout）被进一步限制为减小的第二限制动作。 此外，在输出端短路再复位的情况下，当输出电压（Vout）为检测电压值（Vref2）以上而检测电压值（Vref3）以​​上的值时， 第二限制操作被取消。

公开(公告)号：US07443641B2

公开(公告)日：2008-10-28

申请号：US11521676

申请日：2006-09-14

申请人： Teruo Suzuki

发明人： Teruo Suzuki

IPC分类号： H02H3/24

CPC分类号： H02M3/156 ,  H02M1/32 ,  H02M2001/009

摘要： Provided is a DC-DC converter including a short-circuit protection circuit which can stably perform a reset operation and a stop operation. The short-circuit protection circuit includes a detection circuit, a delay circuit, and a latch circuit. The delay circuit is reset in response to an output voltage abnormality signal related to a switching regulator which is outputted from the latch circuit. The latch circuit is reset based on an AND operation between the output voltage abnormality signal and a UVLO signal.

摘要翻译： 提供一种DC-DC转换器，其包括可以稳定地执行复位操作和停止操作的短路保护电路。 短路保护电路包括检测电路，延迟电路和锁存电路。 响应于与从锁存电路输出的开关调节器相关的输出电压异常信号，延迟电路复位。 基于输出电压异常信号和UVLO信号之间的“与”运算，锁存电路复位。

公开(公告)号：US07199566B2

公开(公告)日：2007-04-03

申请号：US11172682

申请日：2005-07-01

申请人： Teruo Suzuki

发明人： Teruo Suzuki

IPC分类号： G05F1/573 ,  G05F1/00

CPC分类号： G05F1/565

摘要： A voltage regulator has an output transistor connected between a power supply and an output terminal, and a voltage amplifying circuit that compares a feedback voltage with a reference voltage to control the output transistor. A transient response improving circuit has a detecting portion that detects fluctuations in the power supply voltage and controls the operating current of the voltage amplifying circuit based on the detected fluctuation level of the power supply voltage thereby improving the responsiveness and reducing power consumption of the voltage regulator.

摘要翻译： 电压调节器具有连接在电源和输出端子之间的输出晶体管，以及将反馈电压与参考电压进行比较以控制输出晶体管的电压放大电路。 瞬态响应改善电路具有检测部分，其检测电源电压的波动，并根据检测到的电源电压的波动水平控制电压放大电路的工作电流，从而提高电压调节器的响应性和降低功耗 。