公开(公告)号：US06660647B1

公开(公告)日：2003-12-09

申请号：US09646012

申请日：2001-01-11

申请人： Tetsuo Ono ,  Takafumi Tokunaga ,  Tadashi Umezawa ,  Motohiko Yoshigai ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takashi Sato ,  Yasushi Goto

发明人： Tetsuo Ono ,  Takafumi Tokunaga ,  Tadashi Umezawa ,  Motohiko Yoshigai ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takashi Sato ,  Yasushi Goto

IPC分类号： H01L2100

CPC分类号： H01J37/32082 ,  H01L21/32136 ,  H01L21/32139

摘要： A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

摘要翻译： 具有在被处理物质上形成的不含有碳作为主要成分的掩模层的样品的表面处理方法，该物质是沉积在硅基板上的金属，半导体和绝缘体，该物质包括如下步骤： 在真空容器中的样品板上，在真空容器内产生由卤素气体和粘合气体的混合物构成的等离子体，在样品板上施加频率范围为200kHz〜20MHz的射频偏置电压， 以从100Hz到10kHz的开关控制频率来控制射频偏置电压的周期性的断开。

公开(公告)号：US07259104B2

公开(公告)日：2007-08-21

申请号：US10671608

申请日：2003-09-29

申请人： Tetsuo Ono ,  Takafumi Tokunaga ,  Tadashi Umezawa ,  Motohiko Yoshigai ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takashi Sato ,  Yasushi Goto

发明人： Tetsuo Ono ,  Takafumi Tokunaga ,  Tadashi Umezawa ,  Motohiko Yoshigai ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takashi Sato ,  Yasushi Goto

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： H01J37/32082 ,  H01L21/32136 ,  H01L21/32139

摘要： A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

摘要翻译： 具有在被处理物质上形成的不含有碳作为主要成分的掩模层的样品的表面处理方法，该物质是沉积在硅基板上的金属，半导体和绝缘体，该物质包括如下步骤： 在真空容器中的样品板上，在真空容器内产生由卤素气体和粘合气体的混合物构成的等离子体，在样品板上施加频率范围为200kHz〜20MHz的射频偏置电压， 以从100Hz到10kHz的开关控制频率来控制射频偏置电压的周期性的断开。

公开(公告)号：US06677244B2

公开(公告)日：2004-01-13

申请号：US10135516

申请日：2002-05-01

申请人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

发明人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

IPC分类号： H01L21302

CPC分类号： H01J37/32082 ,  H01L21/32136

摘要： A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.

摘要翻译： 用于蚀刻具有栅极氧化膜的样品的等离子体处理方法包括使用电磁波在真空室中产生等离子体，向样品施加rf偏置功率，在样品的充电电压达到击穿之前关闭rf偏置功率 电压，在样品的充电电压基本上下降之后接通rf偏置功率，并且重复接通和关断rf偏置功率以处理样品。 关闭时间至少比准时更长。

公开(公告)号：US07049243B2

公开(公告)日：2006-05-23

申请号：US10754594

申请日：2004-01-12

申请人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

发明人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

IPC分类号： H01L21/302

CPC分类号： H01J37/32082 ,  H01L21/32136

摘要： A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.

摘要翻译： 一种用于蚀刻具有使用电磁波在真空室中产生等离子体的栅极氧化膜的样品的等离子体处理方法，对样品施加rf偏置功率，在样品的充电电压达到击穿之前关断rf偏置功率 栅极氧化膜的电压在样品的充电电压基本上下降之后导通rf偏置功率，并重复rf偏置功率的导通和截止以处理样品。 关断时间至少比导通时间长，并且通过连续供电以在反复打开和关闭rf偏置功率期间产生等离子体而产生等离子体。

公开(公告)号：US06492277B1

公开(公告)日：2002-12-10

申请号：US09393893

申请日：1999-09-10

申请人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

发明人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

IPC分类号： H01L21302

CPC分类号： H01J37/32082 ,  H01L21/32136

摘要： Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.

摘要翻译： 抑制其等离子体蚀刻对半导体元件的电气损伤。 在通过等离子体蚀刻处理精细图案时，在图案的一部分处的电荷电位达到与所述精细图案互连的栅极氧化膜的击穿电压之前，施加到样本的高频电源被关断 ，然后当图案部分的电荷电位基本上下降时，高频电源被接通。 该开启和关闭控制以重复的操作模式进行。

公开(公告)号：US06191045B1

公开(公告)日：2001-02-20

申请号：US09302438

申请日：1999-04-30

申请人： Motohiko Yoshigai ,  Hiroshi Hasegawa ,  Hiroshi Akiyama ,  Takafumi Tokunaga ,  Tadashi Umezawa ,  Masayuki Kojima ,  Kazuo Nojiri ,  Hiroshi Kawakami ,  Kunihiko Katou

发明人： Motohiko Yoshigai ,  Hiroshi Hasegawa ,  Hiroshi Akiyama ,  Takafumi Tokunaga ,  Tadashi Umezawa ,  Masayuki Kojima ,  Kazuo Nojiri ,  Hiroshi Kawakami ,  Kunihiko Katou

IPC分类号： H01L2100

CPC分类号： H01L21/67069 ,  H01L21/32136 ,  H01L21/32137

摘要： In order to provide a method of treating a multilayer including metal and polysilicon for use in a conductor or a gate electrode of a semiconductor device with high accuracy at a high selectivity, the temperature of a sample is maintained at 100° C. or higher at the time of etching a metal film to increase the etch rate of the metal film. In order to suppress the etch rate of a polysilicon film and prevent side etching, an oxygen gas is added to a gas containing a halogen element. In order to suppress the etch rate of a silicon oxide film at the time of etching the polysilicon film, the etching is performed with etch parameters which are divided into those for the metal film and those for the polysilicon film. In the etching performed to the multilayer containing metal and polysilicon, by etching the metal film at a high temperature of 100° C. or higher, the etch rate of the metal film becomes high. Consequently, there is no partial etch residue of the metal film and a barrier film. By switching the parameters to those with which the polysilicon film can be etched at a high selectivity with respect to an oxide film at the time point of completion of etching to the barrier film, very accurate treatment can be realized.

摘要翻译： 为了提供以高选择性以高精度处理用于半导体器件的导体或栅电极的金属和多晶硅的多层的方法，将样品的温度保持在100℃以上 蚀刻金属膜以增加金属膜的蚀刻速率的时间。 为了抑制多晶硅膜的蚀刻速度并防止侧面蚀刻，将氧气添加到含有卤素元素的气体中。 为了抑制蚀刻多晶硅膜时的氧化硅膜的蚀刻速率，用蚀刻参数进行蚀刻，蚀刻参数分为金属膜和多晶硅膜蚀刻参数。 在对多层容纳金属和多晶硅进行的蚀刻中，通过在100℃以上的高温下蚀刻金属膜，金属膜的蚀刻速度变高。 因此，不存在金属膜和阻挡膜的部分蚀刻残留。 通过在对阻挡膜的蚀刻完成时刻将参数切换为能够以相对于氧化膜的高选择性蚀刻多晶硅膜的参数，可以实现非常精确的处理。

公开(公告)号：US20080020495A1

公开(公告)日：2008-01-24

申请号：US11840514

申请日：2007-08-17

申请人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

发明人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

IPC分类号： H01L21/00

CPC分类号： H01J37/32935 ,  H01L21/67069 ,  H01L21/67253

摘要： A semiconductor fabricating method including: placing the semiconductor wafer having a film thereon inside of a chamber; generating plasma; detecting a quantity of interference lights for each of at least two wavelengths obtained from a surface of the wafer for a predetermined time period during the etching of the wafer; detecting a first time point at which the detected quantity of interference lights for one of the two wavelengths becomes a maximum and a second time point at which the detected quantity of interference lights for the other wavelength becomes a minimum; determining a state of etching based on a result of comparing a predetermined value with an interval between the first and second time points, wherein both time points are detected by using outputs of a detector for detecting a quantity of the interference lights; and controlling etching in accordance with the determining.

摘要翻译： 一种半导体制造方法，包括：将其上具有膜的半导体晶片放置在室内; 产生等离子体 在晶片的蚀刻期间，在从晶片表面获得的每个至少两个波长的预定时间段内检测干涉光量; 检测所述检测到的两个波长中的一个波长的干扰光的检测量成为最大的第一时间点和所述其他波长的所检测的干涉光量成为最小的第二时间点; 基于将预定值与第一和第二时间点之间的间隔进行比较的结果来确定蚀刻状态，其中通过使用用于检测干涉光量的检测器的输出来检测两个时间点; 以及根据该确定来控制蚀刻。

公开(公告)号：US20060077397A1

公开(公告)日：2006-04-13

申请号：US11289394

申请日：2005-11-30

申请人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

发明人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

IPC分类号： G01B11/02

CPC分类号： H01J37/32935 ,  H01L21/67069 ,  H01L21/67253

摘要： A semiconductor fabricating apparatus for etching a semiconductor wafer, which is placed in a chamber and which has a multiple-layer film composed of a first film formed on a surface thereof and a second film formed on the first film, using plasma generated in the chamber. The semiconductor fabricating apparatus includes a light detector that detects a change in an amount of light with a plurality of wavelengths obtained from the surface of the wafer for a predetermined time during which the second film is etched, and a detection unit that detects a thickness of the first film based on a specific waveform obtained from an output of the detector.

摘要翻译： 一种用于蚀刻半导体晶片的半导体制造装置，该半导体制造装置被放置在腔室中，并且具有由在其表面上形成的第一膜构成的多层膜和在第一膜上形成的第二膜， 。 半导体制造装置包括：光检测器，其在第二膜被蚀刻的预定时间内检测从晶片的表面获得的多个波长的光量的变化;以及检测单元，其检测厚度 基于从检测器的输出获得的特定波形的第一胶片。

公开(公告)号：US08071397B2

公开(公告)日：2011-12-06

申请号：US11840514

申请日：2007-08-17

申请人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

发明人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

IPC分类号： H01L21/00

CPC分类号： H01J37/32935 ,  H01L21/67069 ,  H01L21/67253

摘要： A semiconductor fabricating method including: placing the semiconductor wafer having a film thereon inside of a chamber; generating plasma; detecting a quantity of interference lights for each of at least two wavelengths obtained from a surface of the wafer for a predetermined time period during the etching of the wafer; detecting a first time point at which the detected quantity of interference lights for one of the two wavelengths becomes a maximum and a second time point at which the detected quantity of interference lights for the other wavelength becomes a minimum; determining a state of etching based on a result of comparing a predetermined value with an interval between the first and second time points, wherein both time points are detected by using outputs of a detector for detecting a quantity of the interference lights; and controlling etching in accordance with the determining.

摘要翻译： 一种半导体制造方法，包括：将其上具有膜的半导体晶片放置在室内; 产生等离子体 在晶片的蚀刻期间，在从晶片表面获得的每个至少两个波长的预定时间段内检测干涉光量; 检测所述检测到的两个波长中的一个波长的干扰光的检测量成为最大的第一时间点和所述其他波长的所检测的干涉光量成为最小的第二时间点; 基于将预定值与第一和第二时间点之间的间隔进行比较的结果来确定蚀刻状态，其中通过使用用于检测干涉光量的检测器的输出来检测两个时间点; 以及根据该确定来控制蚀刻。

公开(公告)号：US06972848B2

公开(公告)日：2005-12-06

申请号：US10377823

申请日：2003-03-04

申请人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

发明人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

IPC分类号： G01B9/02 ,  G01R31/26 ,  H01J37/32

CPC分类号： H01J37/32935 ,  H01L21/67069 ,  H01L21/67253

摘要： When a semiconductor wafer placed in a chamber and having films thereon is etched using plasma generated in the chamber, a change in the amount of lights with at least two wavelengths, obtained from the wafer surface during the processing, is detected. The time between the time at which the amount of a light with one of two wavelengths is maximized and the time at which the amount of a light with the other wavelength is minimized is compared with a predetermined value to determine the state of etching processing.

摘要翻译： 当使用在室中产生的等离子体来刻蚀放置在腔室中并且具有膜上的膜的半导体晶片时，检测在处理期间从晶片表面获得的具有至少两个波长的光量的变化。 将具有两个波长中的一个的光量的时间最大化的时间与其他波长的光量最小化的时间与预定值进行比较，以确定蚀刻处理的状态。