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    Semiconductor device and manufacturing method thereof
    6.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US06818492B2

    公开(公告)日：2004-11-16

    申请号：US10016142

    申请日：2001-12-17

    申请人： Hirotoshi Kubo ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Hidetaka Sawame

    发明人： Hirotoshi Kubo ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Hidetaka Sawame

    IPC分类号： H01L218238

    CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/732

    摘要： This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.

    摘要翻译： 本发明提供一种高频特性优异的半导体器件，其中通过形成在基极区域中的沟槽进行发射极扩散，基极电阻进一步降低，并且基极 - 发射极电容也降低。 基极层与基极区域的整个表面接触。 在基部区域中设置有锥形沟槽。 通过从沟槽的底部的发射体扩散形成更细的发射极区域。 由于基极与沟槽相邻形成，所以可以缩短基极的有源区域与基极层之间的距离，并且还可以获得更大的基极接地面积，因此能够大幅降低基极电阻。 此外，通过形成微细的区域，也可以减小基极和发射极之间的基极 - 发射极电容，因此可以获得高频特性优异的晶体管。

    Field effect transistor semiconductor and method for manufacturing the same
    7.
    发明授权
    Field effect transistor semiconductor and method for manufacturing the same 失效
    场效应晶体管半导体及其制造方法

    公开(公告)号：US06617660B2

    公开(公告)日：2003-09-09

    申请号：US09391507

    申请日：1999-09-08

    申请人： Shigeyuki Murai ,  Emi Fujii ,  Shigeharu Matsushita ,  Hisaaki Tominaga

    发明人： Shigeyuki Murai ,  Emi Fujii ,  Shigeharu Matsushita ,  Hisaaki Tominaga

    IPC分类号： H01L29095

    CPC分类号： H01L29/66871 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/812

    摘要： This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof. The field effect transistor semiconductor of this invention comprises a source/drain electrode 6 positioned in a predetermined position in a GaAs substrate 1, a channel region provided in the GaAs substrate 1 and between the source/drain electrodes 6, a gate electrode 11 which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes 6, and an insulating film 7 which electrically insulates a surface of the GaAs substrate and the gate electrode 11 at both side surfaces of the gate electrode 11. The gate electrode 11 covers a part of the insulating film 7 and the surface of the GaAs substrate serving as the channel region, and a bottom metallic layer 8 contained in the gate electrode 11 is covered with a second metallic layer 9 which is highly adhesive to the insulating film 7.

    摘要翻译： 本发明的目的是提供一种场效应晶体管半导体，其在栅极金属和限定栅电极端的绝缘膜之间具有很大的粘合性，并提高其生产成品率。本发明的场效应晶体管半导体包括源极/漏极 6位于GaAs衬底1中的预定位置，设置在GaAs衬底1中并在源/漏电极6之间的沟道区，与沟道区的一部分肖特基接触并位于 源极/漏极6以及绝缘膜7，其将栅极电极11的两个侧表面处的GaAs衬底的表面和栅极电极11电绝缘。栅电极11覆盖绝缘膜7的一部分，并且 作为沟道区的GaAs衬底的表面和包含在栅极11中的底部金属层8被第二个元件覆盖 与绝缘膜7高度粘合的层9。

    Semiconductor device and manufacturing method thereof
    8.
    发明申请
    Semiconductor device and manufacturing method thereof 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20050167785A1

    公开(公告)日：2005-08-04

    申请号：US11024225

    申请日：2004-12-29

    申请人： Hisaaki Tominaga ,  Keita Odajima ,  Shigehito Matsumoto ,  Masamichi Yamamuro

    发明人： Hisaaki Tominaga ,  Keita Odajima ,  Shigehito Matsumoto ,  Masamichi Yamamuro

    IPC分类号： H01L29/72 ,  H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L29/00

    CPC分类号： H01L29/66287 ,  H01L29/0821 ,  H01L29/7322

    摘要： In a bipolar transistor, an SIC layer is provided right under a genuine base region in order to suppress the Kirk effect and improve fT characteristic by thinning the film of the genuine base region. The higher the concentration of impurities in the SIC layer, the bigger the effect. When the impurity concentration of the SIC layer is high, the VCEO deteriorates so that the fT characteristic improvement and the Kirk effect suppression are in a trade off relationship with the VCEO. A second SIC layer is provided right under the genuine base region and in contact therewith, and a first SIC layer with a higher impurity concentration than the second SIC layer is formed right under the second SIC layer. The first SIC layer narrows the collector width and suppresses the Kirk effect whereas, the second SIC layer makes it possible to improve fT characteristic by cutting a lower edge of the genuine base region. Two SIC layers having varying depths can be formed in one heat treatment by using in the first SIC layer impurities that have a larger diffusion coefficient than the impurities of the second SIC layer.

    摘要翻译： 在双极晶体管中，SIC层设置在真正的基极区域的正下方，以抑制Kirk效应，并且通过使真正的基极区域的膜变薄来提高fT特性。 SIC层杂质浓度越高，效果越好。 当SIC层的杂质浓度高时，VCEO劣化，使得fT特性改善和Kirk效应抑制与VCEO有折衷关系。 第二SIC层设置在真正的基底区域正下方并与之接触，并且在第二SIC层的正下方形成具有比第二SIC层更高的杂质浓度的第一SIC层。 第一个SIC层缩小了收集器的宽度并抑制了柯克效应，而第二个SIC层可以通过切割真正的基底区域的下边缘来提高fT特性。 通过在第一SIC层中使用具有比第二SIC层的杂质更大的扩散系数的杂质，可以在一个热处理中形成具有不同深度的两个SIC层。