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    Field effect transistor semiconductor and method for manufacturing the same
    6.
    发明授权
    Field effect transistor semiconductor and method for manufacturing the same 失效
    场效应晶体管半导体及其制造方法

    公开(公告)号：US06617660B2

    公开(公告)日：2003-09-09

    申请号：US09391507

    申请日：1999-09-08

    申请人： Shigeyuki Murai ,  Emi Fujii ,  Shigeharu Matsushita ,  Hisaaki Tominaga

    发明人： Shigeyuki Murai ,  Emi Fujii ,  Shigeharu Matsushita ,  Hisaaki Tominaga

    IPC分类号： H01L29095

    CPC分类号： H01L29/66871 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/812

    摘要： This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof. The field effect transistor semiconductor of this invention comprises a source/drain electrode 6 positioned in a predetermined position in a GaAs substrate 1, a channel region provided in the GaAs substrate 1 and between the source/drain electrodes 6, a gate electrode 11 which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes 6, and an insulating film 7 which electrically insulates a surface of the GaAs substrate and the gate electrode 11 at both side surfaces of the gate electrode 11. The gate electrode 11 covers a part of the insulating film 7 and the surface of the GaAs substrate serving as the channel region, and a bottom metallic layer 8 contained in the gate electrode 11 is covered with a second metallic layer 9 which is highly adhesive to the insulating film 7.

    摘要翻译： 本发明的目的是提供一种场效应晶体管半导体，其在栅极金属和限定栅电极端的绝缘膜之间具有很大的粘合性，并提高其生产成品率。本发明的场效应晶体管半导体包括源极/漏极 6位于GaAs衬底1中的预定位置，设置在GaAs衬底1中并在源/漏电极6之间的沟道区，与沟道区的一部分肖特基接触并位于 源极/漏极6以及绝缘膜7，其将栅极电极11的两个侧表面处的GaAs衬底的表面和栅极电极11电绝缘。栅电极11覆盖绝缘膜7的一部分，并且 作为沟道区的GaAs衬底的表面和包含在栅极11中的底部金属层8被第二个元件覆盖 与绝缘膜7高度粘合的层9。

    Semiconductor device and manufacturing method thereof
    7.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US06818492B2

    公开(公告)日：2004-11-16

    申请号：US10016142

    申请日：2001-12-17

    申请人： Hirotoshi Kubo ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Hidetaka Sawame

    发明人： Hirotoshi Kubo ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Hidetaka Sawame

    IPC分类号： H01L218238

    CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/732

    摘要： This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.

    摘要翻译： 本发明提供一种高频特性优异的半导体器件，其中通过形成在基极区域中的沟槽进行发射极扩散，基极电阻进一步降低，并且基极 - 发射极电容也降低。 基极层与基极区域的整个表面接触。 在基部区域中设置有锥形沟槽。 通过从沟槽的底部的发射体扩散形成更细的发射极区域。 由于基极与沟槽相邻形成，所以可以缩短基极的有源区域与基极层之间的距离，并且还可以获得更大的基极接地面积，因此能够大幅降低基极电阻。 此外，通过形成微细的区域，也可以减小基极和发射极之间的基极 - 发射极电容，因此可以获得高频特性优异的晶体管。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07399999B2

    公开(公告)日：2008-07-15

    申请号：US10958640

    申请日：2004-10-06

    申请人： Tetsuya Yoshida ,  Tetsuya Okada ,  Hiroaki Saito ,  Shigeyuki Murai ,  Kikuo Okada

    发明人： Tetsuya Yoshida ,  Tetsuya Okada ,  Hiroaki Saito ,  Shigeyuki Murai ,  Kikuo Okada

    IPC分类号： H01L29/06

    CPC分类号： H01L29/7397 ,  H01L29/0619

    摘要： In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 Å. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.

    摘要翻译： 在传统的半导体器件中，存在在保护环区域中耗尽层的形状变形而不能得到稳定的耐电压特性的问题。 在本发明的半导体装置中，以相同的工序形成实际工作区域中的热氧化膜和防护环区域的热氧化膜。 此后，热氧化膜被一次除去并再次形成。 因此，保护​​环区域的上表面上的热氧化膜的膜厚设定为例如约8000〜10000。 因此，包含移动离子的CVD氧化膜形成在远离外延层的表面的位置。 因此，受到移动离子影响的耗尽层的失真被抑制，并且可以保持期望的耐受电压特性。

    Semiconductor device
    9.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20050116283A1

    公开(公告)日：2005-06-02

    申请号：US10968354

    申请日：2004-10-20

    申请人： Tetsuya Yoshida ,  Tetsuya Okada ,  Hiroaki Saito ,  Shigeyuki Murai ,  Kikuo Okada

    发明人： Tetsuya Yoshida ,  Tetsuya Okada ,  Hiroaki Saito ,  Shigeyuki Murai ,  Kikuo Okada

    IPC分类号： H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78 ,  H01L29/80

    CPC分类号： H01L29/7828 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/4916

    摘要： In conventional semiconductor devices, there observed a problem that cells on the devices may not function uniformly because of voltage drop in a main wiring layer due to a uniform and narrow width of the main wiring layer through which a main current flows. In a semiconductor device of the present invention, a width of one end of a main wire for carrying the main current is formed wider than a width of another end of the main wire. An overall width of the main wire is formed so as to be gradually narrowed from the one end to the another end. In this way, it is possible to reduce a difference in drive voltages between a cell located in the vicinity of an electrode pad for carrying the main current and a cell located in a remote position. Resultantly, it is possible to suppress a voltage drop in the main wire and to achieve uniform operations of cells in an element.

    摘要翻译： 在传统的半导体器件中，由于主电流流过的主布线层的宽度均匀而窄，主要布线层中的电压下降，存在器件的电池不能均匀地发挥作用的问题。 在本发明的半导体器件中，用于承载主电流的主线的一端的宽度形成为比主线的另一端的宽度宽。 主线的总宽度形成为从一端到另一端逐渐变窄。 以这种方式，可以减小位于用于承载主电流的电极焊盘附近的电池与位于远程位置的电池之间的驱动电压的差异。 因此，可以抑制主线中的电压降，并实现元件中的电池的均匀操作。

    Method of designing a high-frequency circuit
    10.
    发明授权
    Method of designing a high-frequency circuit 失效
    高频电路设计方法

    公开(公告)号：US5528509A

    公开(公告)日：1996-06-18

    申请号：US214821

    申请日：1994-03-17

    申请人： Tetsuro Sawai ,  Shigeyuki Murai ,  Tsutomu Yamaguchi ,  Yasoo Harada

    发明人： Tetsuro Sawai ,  Shigeyuki Murai ,  Tsutomu Yamaguchi ,  Yasoo Harada

    IPC分类号： H03F1/02 ,  G06F17/50 ,  H03G3/00 ,  H03F3/16

    CPC分类号： G06F17/5063

    摘要： The S-parameters of a transistor are measured at a plurality of bias points, and using a tentatively decided load resistance value, the S-parameters on the load curve are examined, based on which the power gain and input/output power characteristics are obtained to determine the optimum load. Then, by using a linear simulator, input and output circuits are designed so that the optimum load can be realized.

    摘要翻译： 在多个偏置点测量晶体管的S参数，并且使用暂时确定的负载电阻值，检查负载曲线上的S参数，基于该参数获得功率增益和输入/输出功率特性 以确定最佳负载。 然后，通过使用线性模拟器，设计输入和输出电路，以便实现最佳负载。