公开(公告)号：US20170271269A1

公开(公告)日：2017-09-21

申请号：US15615963

申请日：2017-06-07

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/53238 ,  H01L21/31111 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76861 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

公开(公告)号：US10665543B2

公开(公告)日：2020-05-26

申请号：US16010642

申请日：2018-06-18

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

公开(公告)号：US10008450B2

公开(公告)日：2018-06-26

申请号：US15615963

申请日：2017-06-07

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/31111 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76861 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L24/00 ,  H01L2224/05624

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

公开(公告)号：US09305998B2

公开(公告)日：2016-04-05

申请号：US14175838

申请日：2014-02-07

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Eric H. Warninghoff ,  Alan Merriam ,  Haowen Bu ,  Brian E. Goodlin ,  Manoj K. Jain

IPC: H01L21/00 ,  H01L49/02 ,  H01L21/02 ,  C23C16/02 ,  C23C16/40 ,  H01L27/115

CPC classification number: H01L28/75 ,  C23C16/0281 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/02304 ,  H01L27/11502 ,  H01L28/55

Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

Abstract translation: 在铱金属上沉积钛酸锆（PZT）铁电材料，在集成电路中形成铁电电容器。 通过沉积具有铱金属的下导电板层作为顶层形成电容器。 铱金属的表面在PZT材料沉积之前或期间被热氧化。 在铱金属表面的所得铱氧化物非常薄，几毫米数量级，这允许沉积的PZT根据铱金属的晶体结构而不是氧化铱的晶体结构成核。 氧化铱也具有中等化学计量（IrO2-x），并与沉积的PZT材料发生反应。

公开(公告)号：US20140227805A1

公开(公告)日：2014-08-14

申请号：US14175838

申请日：2014-02-07

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Eric H. Warninghoff ,  Alan Merriam ,  Haowen Bu ,  Brian E. Goodlin ,  Manoj K. Jain

IPC: H01L49/02

CPC classification number: H01L28/75 ,  C23C16/0281 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/02304 ,  H01L27/11502 ,  H01L28/55

Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

Abstract translation: 在铱金属上沉积钛酸锆（PZT）铁电材料，在集成电路中形成铁电电容器。 通过沉积具有铱金属的下导电板层作为顶层形成电容器。 铱金属的表面在PZT材料沉积之前或期间被热氧化。 在铱金属表面的所得铱氧化物非常薄，几毫米数量级，这允许沉积的PZT根据铱金属的晶体结构而不是氧化铱的晶体结构成核。 氧化铱也具有中等化学计量（IrO2-x），并与沉积的PZT材料发生反应。

公开(公告)号：US20180308802A1

公开(公告)日：2018-10-25

申请号：US16010642

申请日：2018-06-18

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

公开(公告)号：US09704804B1

公开(公告)日：2017-07-11

申请号：US14974012

申请日：2015-12-18

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L21/44 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L23/53238 ,  H01L21/31111 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76861 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

公开(公告)号：US20170179033A1

公开(公告)日：2017-06-22

申请号：US14974012

申请日：2015-12-18

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L23/532 ,  H01L21/311 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/31111 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76861 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.