公开(公告)号：US09515667B2

公开(公告)日：2016-12-06

申请号：US14587951

申请日：2014-12-31

Applicant: Texas Instruments Incorporated

Inventor： Sreekiran Samala ,  Vineet Mishra ,  Mahadevan Shankara Venkiteswaran

IPC: H03L7/099 ,  H03B5/24 ,  H03L1/02 ,  H03L7/095 ,  H03L7/18

CPC classification number: H03L7/0995 ,  H03B5/24 ,  H03K3/0231 ,  H03L1/026 ,  H03L7/095 ,  H03L7/099 ,  H03L7/104 ,  H03L7/18

Abstract: Circuitry for providing an oscillating output signal. The circuitry comprises a transconductance circuit having a first input, a second input, and an output. The circuitry further comprises an oscillator circuit coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit. Also included are circuitry for providing a first voltage to the first input of the transconductance circuit and a frequency controlled circuit for providing a second voltage to the second input the transconductance circuit. The second voltage is response to a frequency of operation of the frequency controlled circuit, and the frequency of operation of the frequency controlled circuit is responsive to feedback from the output of the oscillator circuit.

Abstract translation: 提供振荡输出信号的电路。 电路包括具有第一输入，第二输入和输出的跨导电路。 电路还包括耦合以从跨导电路的输出接收电压的振荡器电路，其中振荡输出信号响应振荡器电路的输出。 还包括用于向跨导电路的第一输入提供第一电压的电路和用于向第二输入提供跨导电路的第二电压的频率控制电路。 第二电压响应于频率控制电路的工作频率，频率控制电路的工作频率响应于来自振荡器电路的输出的反馈。

公开(公告)号：US08698546B1

公开(公告)日：2014-04-15

申请号：US13625609

申请日：2012-09-24

Applicant: Texas Instruments Incorporated

Inventor： Vineet Mishra ,  Rajavelu Thinakaran

IPC: H03K17/16

CPC classification number: H03K17/6871 ,  H03K17/04123 ,  H03K17/102 ,  H03K2217/0009 ,  H03K2217/0054

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

公开(公告)号：US09362939B1

公开(公告)日：2016-06-07

申请号：US14587825

申请日：2014-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shakti Shankar Rath ,  Rishubh Khurana ,  Vineet Mishra

IPC: H03M1/14 ,  H03M1/46 ,  H03M1/00 ,  H03M1/36

CPC classification number: H03M1/468 ,  H03M1/0614 ,  H03M1/145 ,  H03M1/361

Abstract: Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom.

Abstract translation: 公开了用于减少闪光逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）中的输入相关电容器DAC切换电流的电路和方法。 ADC包括M位闪存ADC和N位SAR ADC。 在闪存转换阶段，闪存ADC输出数字信号，包括采样模拟信号的数字输出代码的N位最高有效M位。 SAR ADC包括电容DAC和数字引擎。 电容器DAC包括第一和第二组电容器，其中第一和第二组电容器的第一端耦合到公共端子。 数字引擎基于数字信号和公共端的电压（Vcom），在SAR转换阶段提供数字输出代码的N位。 在闪光转换阶段期间，第一组电容器的第二端分别连接到Vref和Vgnd，以便产生与数字信号对应的电压电平为Vcom。

公开(公告)号：US08766700B1

公开(公告)日：2014-07-01

申请号：US14197320

申请日：2014-03-05

Applicant: Texas Instruments Incorporated

Inventor： Vineet Mishra ,  Rajavelu Thinakaran

IPC: H03K17/16

CPC classification number: H03K17/6871 ,  H03K17/04123 ,  H03K17/102 ,  H03K2217/0009 ,  H03K2217/0054

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract translation: 采样的CMOS开关包括在输入和输出节点之间串联的第一和第二NMOS器件。 第一和第二NMOS器件由采样信号激活。 一对低电压DEPMOS器件以“T”配置连接在输入和输出节点之间。 低电压DEPMOS器件由反向采样信号激活。 反馈电路包括DEPMOS器件以及第三高电压NMOS器件和电流源。 第三NMOS器件由输入节点上的信号控制。 开关根据反相采样信号的相位可切换地将模拟电压源连接到第三NMOS器件的源极和DEPMOS器件的栅极。 采样CMOS开关的结构使得能够保护低压DEPMOS晶体管的栅极氧化物绝缘体免受高压损坏。

公开(公告)号：US20160191072A1

公开(公告)日：2016-06-30

申请号：US14587825

申请日：2014-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shakti Shankar Rath ,  Rishubh Khurana ,  Vineet Mishra

IPC: H03M1/46 ,  H03M1/36 ,  H03M1/00

CPC classification number: H03M1/468 ,  H03M1/0614 ,  H03M1/145 ,  H03M1/361

Abstract: Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom.

Abstract translation: 公开了用于减少闪光逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）中的输入相关电容器DAC切换电流的电路和方法。 ADC包括M位闪存ADC和N位SAR ADC。 在闪存转换阶段，闪存ADC输出数字信号，包括采样模拟信号的数字输出代码的N位最高有效M位。 SAR ADC包括电容DAC和数字引擎。 电容器DAC包括第一和第二组电容器，其中第一和第二组电容器的第一端耦合到公共端子。 数字引擎基于数字信号和公共端的电压（Vcom），在SAR转换阶段提供数字输出代码的N位。 在闪光转换阶段期间，第一组电容器的第二端分别连接到Vref和Vgnd，以便产生与数字信号对应的电压电平为Vcom。

公开(公告)号：US20160191067A1

公开(公告)日：2016-06-30

申请号：US14587951

申请日：2014-12-31

Applicant: Texas Instruments Incorporated

Inventor： Sreekiran Samala ,  Vineet Mishra ,  Mahadevan Shankara Venkiteswaran

IPC: H03L7/099 ,  H03B5/24

CPC classification number: H03L7/0995 ,  H03B5/24 ,  H03K3/0231 ,  H03L1/026 ,  H03L7/095 ,  H03L7/099 ,  H03L7/104 ,  H03L7/18

Abstract: Circuitry for providing an oscillating output signal. The circuitry comprises a transconductance circuit having a first input, a second input, and an output. The circuitry further comprises an oscillator circuit coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit. Also included are circuitry for providing a first voltage to the first input of the transconductance circuit and a frequency controlled circuit for providing a second voltage to the second input the transconductance circuit. The second voltage is response to a frequency of operation of the frequency controlled circuit, and the frequency of operation of the frequency controlled circuit is responsive to feedback from the output of the oscillator circuit.

Abstract translation: 提供振荡输出信号的电路。 电路包括具有第一输入，第二输入和输出的跨导电路。 电路还包括耦合以从跨导电路的输出接收电压的振荡器电路，其中振荡输出信号响应振荡器电路的输出。 还包括用于向跨导电路的第一输入提供第一电压的电路和用于向第二输入提供跨导电路的第二电压的频率控制电路。 第二电压响应于频率控制电路的工作频率，并且频率控制电路的工作频率响应于来自振荡器电路的输出的反馈。

公开(公告)号：US20140184310A1

公开(公告)日：2014-07-03

申请号：US14197320

申请日：2014-03-05

Applicant: Texas Instruments Incorporated

Inventor： Vineet Mishra ,  Rajavelu Thinakaran

IPC: H03K17/687

CPC classification number: H03K17/6871 ,  H03K17/04123 ,  H03K17/102 ,  H03K2217/0009 ,  H03K2217/0054

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract translation: 采样的CMOS开关包括在输入和输出节点之间串联的第一和第二NMOS器件。 第一和第二NMOS器件由采样信号激活。 一对低电压DEPMOS器件以“T”配置连接在输入和输出节点之间。 低电压DEPMOS器件由反向采样信号激活。 反馈电路包括DEPMOS器件以及第三高电压NMOS器件和电流源。 第三NMOS器件由输入节点上的信号控制。 开关根据反相采样信号的相位可切换地将模拟电压源连接到第三NMOS器件的源极和DEPMOS器件的栅极。 采样CMOS开关的结构使得能够保护低压DEPMOS晶体管的栅极氧化物绝缘体免受高压损坏。

公开(公告)号：US20140084988A1

公开(公告)日：2014-03-27

申请号：US13625609

申请日：2012-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vineet Mishra ,  Rajavelu Thinakaran

IPC: H03K17/687

CPC classification number: H03K17/6871 ,  H03K17/04123 ,  H03K17/102 ,  H03K2217/0009 ,  H03K2217/0054

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.