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17 条记录 (耗时 0.025 秒)

    Method and apparatus for detecting potential lock-up conditions in a video graphics controller
    1.
    发明授权
    Method and apparatus for detecting potential lock-up conditions in a video graphics controller 失效
    用于检测视频图形控制器中的潜在锁定条件的方法和装置

    公开(公告)号：US06819322B2

    公开(公告)日：2004-11-16

    申请号：US10038009

    申请日：2002-01-04

    申请人： Theodore F. Emerson ,  Robert L. Noonan ,  Don A. Dykes

    发明人： Theodore F. Emerson ,  Robert L. Noonan ,  Don A. Dykes

    IPC分类号： G06F1314

    CPC分类号： G06F3/1454 ,  G09G5/39 ,  G09G2310/04 ,  G09G2340/02

    摘要： Certain accesses by a processor to a video graphics controller may cause concurrent accesses by a remote management controller to cause the video graphics controller to lock up. To detect potential lock-up events, the remote management controller snoops the bus to determine whether the processor is performing a type of access that could lead to a potential lock-up condition. If so, the remote management controller ceases accessing the bus until the video graphics controller is in an available state.

    摘要翻译： 处理器对视频图形控制器的某些访问可能导致远程管理控制器的并发访问以使视频图形控制器锁定。 为了检测潜在的锁定事件，远程管理控制器侦听总线以确定处理器是否正在执行可能导致潜在锁定状态的访问类型。 如果是这样，远程管理控制器停止访问总线，直到视频图形控制器处于可用状态。

    Mechanisms to prevent undesirable bus behavior
    5.
    发明授权
    Mechanisms to prevent undesirable bus behavior 有权
    防止不必要的总线行为的机制

    公开(公告)号：US07577877B2

    公开(公告)日：2009-08-18

    申请号：US10444154

    申请日：2003-05-22

    申请人： Theodore F. Emerson ,  Phyllis L. Bongain ,  Cesar Buentello ,  Jennifer C. Kleiman ,  Doron Chosnek ,  Robert L. Noonan ,  David F. Heinrich

    发明人： Theodore F. Emerson ,  Phyllis L. Bongain ,  Cesar Buentello ,  Jennifer C. Kleiman ,  Doron Chosnek ,  Robert L. Noonan ,  David F. Heinrich

    IPC分类号： G06F11/00

    CPC分类号： G06F13/423 ,  G06F2213/0024

    摘要： A system includes proxy logic which detects situations which, unless action is taken, would result in undesirable bus behavior. In one embodiment, the target device of a bus cycle includes proxy logic which determines when the target device is unable to respond correctly to a bus cycle. In this situation, the proxy logic blocks a bus signal from being received by the addressed logic in the target device, thereby preventing the target device from responding at all. In another embodiment, proxy logic is located external to the target device and determines when the target device has not responded to a cycle intended for it. When this condition has occurred, the proxy logic responds to the cycle before the bus's subtractive decode agent has a chance to claim the cycle. The proxy logic's response may be to return bogus data or terminate or abort the cycle.

    摘要翻译： 系统包括代理逻辑，其检测除非采取行动之外将导致不期望的总线行为的情况。 在一个实施例中，总线周期的目标设备包括代理逻辑，其确定目标设备何时不能正确响应于总线周期。 在这种情况下，代理逻辑阻止总线信号被目标设备中寻址的逻辑接收，从而防止目标设备完全响应。 在另一个实施例中，代理逻辑位于目标设备的外部，并且确定目标设备何时没有响应于为其预期的循环。 当这种情况发生时，代理逻辑在总线的减法解码器有机会要求循环之前响应周期。 代理逻辑的响应可能是返回虚假数据或终止或中止周期。

    Method and apparatus for capturing and transmitting screen images
    6.
    发明授权
    Method and apparatus for capturing and transmitting screen images 有权
    用于捕获和发送屏幕图像的方法和装置

    公开(公告)号：US07518614B2

    公开(公告)日：2009-04-14

    申请号：US11210082

    申请日：2005-08-23

    申请人： Theodore F. Emerson ,  Robert L. Noonan ,  David F. Heinrich ,  Don Dykes

    发明人： Theodore F. Emerson ,  Robert L. Noonan ,  David F. Heinrich ,  Don Dykes

    IPC分类号： G06T15/00

    CPC分类号： G06F3/1454 ,  G06F3/1462 ,  G06F11/2294 ,  G09G2340/02 ,  H04L1/0061 ,  H04L1/0072 ,  H04L2001/0094 ,  H04N19/132 ,  H04N19/137 ,  H04N19/164 ,  H04N19/174 ,  H04N19/176 ,  H04N19/42 ,  H04N19/436 ,  H04N19/507 ,  H04N21/4334 ,  H04N21/6332

    摘要： A remote management controller may include a video redirection device and a processor. The video redirection device may be configured to: obtain multiple separate slices of video data output from a video graphics controller; calculate at least one value correlative to each of the multiple separate slices of video data; and if the calculated value for any portion of any of the multiple separate slices differs from a value for a previously obtained corresponding portion, update a table associated with an image related to a remote system with the calculated value, process the portion of the slice into a network packet, and move the network packet to one of multiple network buffers. The processor may be configured to: allocate the multiple network buffers; and facilitate transmission of the network packets loaded into the network buffers to the remote system.

    摘要翻译： 远程管理控制器可以包括视频重定向设备和处理器。 视频重定向设备可以被配置为：获得从视频图形控制器输出的多个分离的视频数据片; 计算与视频数据的多个分离片段中的每一个相关的至少一个值; 并且如果多个分离的片段中的任一个的任何部分的计算值与先前获得的相应部分的值不同，则使用计算的值来更新与与远程系统相关的图像相关联的表，将片段的部分处理为 网络分组，并将网络分组移动到多个网络缓冲器之一。 处理器可以被配置为：分配多个网络缓冲器; 并且便于将加载到网络缓冲器中的网络分组传输到远程系统。

    Storing data in any of a plurality of buffers in a memory controller
    7.
    发明授权
    Storing data in any of a plurality of buffers in a memory controller 有权
    将数据存储在存储器控制器中的多个缓冲器中的任一个中

    公开(公告)号：US09213545B2

    公开(公告)日：2015-12-15

    申请号：US13641567

    申请日：2010-06-22

    申请人： Hung Q. Le ,  Theodore F. Emerson ,  David F. Heinrich ,  Robert L. Noonan

    发明人： Hung Q. Le ,  Theodore F. Emerson ,  David F. Heinrich ,  Robert L. Noonan

    IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F9/06 ,  G06F13/16

    CPC分类号： G06F9/06 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/1673

    摘要： A memory controller containing one or more ports coupled to a buffer selection logic and a plurality of buffers. Each buffer is configured to store write data associated with a write request and each buffer is also coupled to the buffer selection logic. The buffer selection logic is configured to store write data associated with a write request from at least one of the ports in any of the buffers based on a priority of the buffers for each one of the ports.

    摘要翻译： 存储器控制器，其包含耦合到缓冲器选择逻辑和多个缓冲器的一个或多个端口。 每个缓冲器被配置为存储与写请求相关联的写入数据，并且每个缓冲器也耦合到缓冲器选择逻辑。 缓冲器选择逻辑被配置为基于每个端口的缓冲器的优先级来存储与来自任何缓冲器中的至少一个端口的写入请求相关联的写入数据。

    STORING DATA IN ANY OF A PLURALITY OF BUFFERS IN A MEMORY CONTROLLER
    8.
    发明申请
    STORING DATA IN ANY OF A PLURALITY OF BUFFERS IN A MEMORY CONTROLLER 有权
    在存储器控制器中存储多个缓冲器的数据

    公开(公告)号：US20130046933A1

    公开(公告)日：2013-02-21

    申请号：US13641567

    申请日：2010-06-22

    申请人： Hung Q. Le ,  Theodore F. Emerson ,  David F. Heinrich ,  Robert L. Noonan

    发明人： Hung Q. Le ,  Theodore F. Emerson ,  David F. Heinrich ,  Robert L. Noonan

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F9/06 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/1673

    摘要： A memory controller containing one or more ports coupled to a buffer selection logic and a plurality of buffers. Each buffer is configured to store write data associated with a write request and each buffer is also coupled to the buffer selection logic. The buffer selection logic is configured to store write data associated with a write request from at least one of the ports in any of the buffers based on a priority of the buffers for each one of the ports.

    摘要翻译： 存储器控制器，其包含耦合到缓冲器选择逻辑和多个缓冲器的一个或多个端口。 每个缓冲器被配置为存储与写请求相关联的写入数据，并且每个缓冲器也耦合到缓冲器选择逻辑。 缓冲器选择逻辑被配置为基于每个端口的缓冲器的优先级来存储与来自任何缓冲器中的至少一个端口的写入请求相关联的写入数据。