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    HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING
    1.
    发明申请
    HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING 有权

    公开(公告)号：US20070254412A1

    公开(公告)日：2007-11-01

    申请号：US11380692

    申请日：2006-04-28

    申请人： Thomas Dyer ,  Haining Yang

    发明人： Thomas Dyer ,  Haining Yang

    IPC分类号： H01L21/8232 ,  H01L29/76

    CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

    摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

    PATTERN ENHANCEMENT BY CRYSTALLOGRAPHIC ETCHING
    2.
    发明申请
    PATTERN ENHANCEMENT BY CRYSTALLOGRAPHIC ETCHING 有权
    晶体蚀刻的图案增强

    公开(公告)号：US20070072429A1

    公开(公告)日：2007-03-29

    申请号：US11162800

    申请日：2005-09-23

    申请人： Thomas Dyer ,  Kenneth Settlemyer ,  James Toomey ,  Haining Yang

    发明人： Thomas Dyer ,  Kenneth Settlemyer ,  James Toomey ,  Haining Yang

    IPC分类号： C23F1/00 ,  H01L21/311 ,  H01L21/302 ,  B44C1/22

    CPC分类号： H01L21/30608 ,  H01L21/32134

    摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

    摘要翻译： 与使用本发明的方法形成的结构一起设置在具有基本上均匀的直边或边缘以及明确限定的内角和外角的含Si结晶材料中产生预定形状的方法。 本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。 由于使用了常规处理，所以图案具有圆角的固有限制。 使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

    METHOD FOR FORMING SELF-ALIGNED, DUAL SILICON NITRIDE LINER FOR CMOS DEVICES
    3.
    发明申请
    METHOD FOR FORMING SELF-ALIGNED, DUAL SILICON NITRIDE LINER FOR CMOS DEVICES 失效
    用于形成用于CMOS器件的自对准的双硅氮化物衬底的方法

    公开(公告)号：US20060199320A1

    公开(公告)日：2006-09-07

    申请号：US10906670

    申请日：2005-03-01

    申请人： Thomas Dyer ,  Haining Yang

    发明人： Thomas Dyer ,  Haining Yang

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/7843

    摘要： A method for forming a self-aligned, dual silicon nitride liner for CMOS devices includes forming a first type nitride layer over a first polarity type device and a second polarity type device, and forming a topographic layer over the first type nitride layer. Portions of the first type nitride layer and the topographic layer over the second polarity type device are patterned and removed. A second type nitride layer is formed over the second polarity type device, and over remaining portions of the topographic layer over the first polarity type device so as to define a vertical pillar of second type nitride material along a sidewall of the topographic layer, the second type nitride layer in contact with a sidewall of the first type nitride layer. The topographic layer is removed and the vertical pillar is removed.

    摘要翻译： 用于形成用于CMOS器件的自对准双氮化硅衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一氮化物层，并在第一氮化物层上形成形貌层。 第一类型氮化物层和第二极性类型器件上的形貌层的部分被图案化和去除。 在第二极性类型器件上形成第二类型氮化物层，并且在第一极性类型器件上方形成地形层的剩余部分，以沿着地形层的侧壁限定第二类型氮化物材料的垂直柱，第二 氮化物层与第一氮化物层的侧壁接触。 去除地形层并移除垂直柱。

    HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING
    4.
    发明申请
    HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING 有权
    高性能3D FET结构及其使用优选结晶蚀刻形成其的方法

    公开(公告)号：US20070298552A1

    公开(公告)日：2007-12-27

    申请号：US11851464

    申请日：2007-09-07

    申请人： Thomas Dyer ,  Haining Yang

    发明人： Thomas Dyer ,  Haining Yang

    IPC分类号： H01L21/84

    CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

    摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

    摘要翻译： 本发明涉及高性能三维（3D）场效应晶体管（FET）。 具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。 更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。 附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。

    IMPROVED SOI SUBSTRATES AND SOI DEVICES, AND METHODS FOR FORMING THE SAME
    5.
    发明申请
    IMPROVED SOI SUBSTRATES AND SOI DEVICES, AND METHODS FOR FORMING THE SAME 失效
    改进的SOI衬底和SOI器件及其形成方法

    公开(公告)号：US20070218603A1

    公开(公告)日：2007-09-20

    申请号：US11308292

    申请日：2006-03-15

    申请人： Thomas Dyer ,  Zhijiong Luo ,  Haining Yang

    发明人： Thomas Dyer ,  Zhijiong Luo ,  Haining Yang

    IPC分类号： H01L21/84

    CPC分类号： H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

    摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.

    摘要翻译： 提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。 具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分 从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）。 例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

    CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS AND METHOD FOR FABRICATING THE SAME
    6.
    发明申请
    CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS AND METHOD FOR FABRICATING THE SAME 有权
    具有混合通道方向的CMOS器件及其制造方法

    公开(公告)号：US20070181980A1

    公开(公告)日：2007-08-09

    申请号：US11307481

    申请日：2006-02-09

    申请人： Thomas Dyer ,  Xiangdong Chen ,  James Toomey ,  Haining Yang

    发明人： Thomas Dyer ,  Xiangdong Chen ,  James Toomey ,  Haining Yang

    IPC分类号： H01L29/04

    CPC分类号： H01L21/823807 ,  H01L21/82385 ,  H01L21/823857

    摘要： The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region comprises a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed at the first device region, which comprises a channel that extends along the interior surfaces of the first recess. At least one p-channel field effect transistor (p-FET) can be formed at the second device region, which comprises a channel that extends along the interior surfaces of the second recess.

    摘要翻译： 本发明涉及包括至少第一和第二器件区域的半导体衬底，其中第一器件区域包括具有沿着第一组等效晶面取向的内表面的第一凹槽，并且其中第二器件区域包括第二凹部， 沿着第二不同组的等效晶面取向的内表面。 可以使用这种半导体衬底形成半导体器件结构。 具体而言，可以在第一器件区域形成至少一个n沟道场效应晶体管（n-FET），该第一器件区域包括沿着第一凹槽的内表面延伸的沟道。 至少一个p沟道场效应晶体管（p-FET）可以在第二器件区域形成，该第二器件区域包括沿着第二凹槽的内表面延伸的沟道。

    CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS AND METHOD FOR FABRICATING THE SAME
    7.
    发明申请
    CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS AND METHOD FOR FABRICATING THE SAME 有权
    具有混合通道方向的CMOS器件及其制造方法

    公开(公告)号：US20080096339A1

    公开(公告)日：2008-04-24

    申请号：US11968479

    申请日：2008-01-02

    申请人： Thomas Dyer ,  Xiangdong Chen ,  James Toomey ,  Haining Yang

    发明人： Thomas Dyer ,  Xiangdong Chen ,  James Toomey ,  Haining Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/82385 ,  H01L21/823857

    摘要： The present invention relates to a method of fabricating a semiconductor substrate that includes forming at least first and second device regions, wherein the first device region includes a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region includes a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. The semiconductor device structure formed using such a semiconductor substrate includes at least one n-channel field effect transistor (n-FET) formed at the first device region having a channel that extends along the interior surfaces of the first recess, and at least one p-channel field effect transistor (p-FET) formed at the second device region having a channel that extends along the interior surfaces of the second recess.

    摘要翻译： 本发明涉及一种制造半导体衬底的方法，该方法包括形成至少第一和第二器件区域，其中第一器件区域包括具有沿第一组等效晶面取向的内表面的第一凹槽，并且其中第二器件 区域包括具有沿着第二不同组的等效晶面取向的内表面的第二凹部。 使用这种半导体衬底形成的半导体器件结构包括形成在第一器件区域处的至少一个n沟道场效应晶体管（n-FET），具有沿着第一凹部的内表面延伸的沟道，以及至少一个p - 沟道场效应晶体管（p-FET），其形成在具有沿着第二凹部的内表面延伸的沟道的第二器件区域处。

    Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior
    9.
    发明授权
    Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior 有权
    采用具有对称电气行为的物理不对称半导体器件的系统和方法

    公开(公告)号：US08558320B2

    公开(公告)日：2013-10-15

    申请号：US12638557

    申请日：2009-12-15

    申请人： Haining Yang ,  Chock H. Gan ,  Zhongze Wang ,  Beom-Mo Han

    发明人： Haining Yang ,  Chock H. Gan ,  Zhongze Wang ,  Beom-Mo Han

    IPC分类号： H01L27/092

    CPC分类号： H01L27/0207 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.

    摘要翻译： 一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。 集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。 导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。 导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

    Semiconductor device having strain material
    10.
    发明授权
    Semiconductor device having strain material 有权
    半导体器件具有应变材料

    公开(公告)号：US08159009B2

    公开(公告)日：2012-04-17

    申请号：US12621736

    申请日：2009-11-19

    申请人： Haining Yang

    发明人： Haining Yang

    IPC分类号： H01L29/78

    CPC分类号： H01L27/088 ,  H01L21/02107 ,  H01L21/486 ,  H01L21/76224 ,  H01L21/823807 ,  H01L27/112 ,  H01L27/1122 ,  H01L29/78 ,  H01L29/7843 ,  H03K17/687

    摘要： A semiconductor device having strain material is disclosed. In a particular embodiment, the semiconductor device includes a first cell including a first gate between a first drain and a first source. The semiconductor device also includes a second cell adjacent to the first cell. The second cell includes a second gate between a second drain and a second source. The semiconductor device further includes a shallow trench isolation area between the first source and the second source. A first amount of strain material over the first source and over the second source is greater than a second amount of strain material over the first drain and over the second drain.

    摘要翻译： 公开了一种具有应变材料的半导体器件。 在特定实施例中，半导体器件包括第一单元，其包括在第一漏极和第一源极之间的第一栅极。 半导体器件还包括与第一单元相邻的第二单元。 第二单元包括在第二漏极和第二源极之间的第二栅极。 半导体器件还包括在第一源极和第二源极之间的浅沟槽隔离区域。 在第一源和第二源上的第一量的应变材料大于在第一漏极和第二漏极上方的第二量的应变材料。