Hearing aid device incorporating signal processing techniques
    1.
    发明授权
    Hearing aid device incorporating signal processing techniques 失效
    含有信号处理技术的助听器

    公开(公告)号:US06072885A

    公开(公告)日:2000-06-06

    申请号:US697412

    申请日:1996-08-22

    IPC分类号: H04R1/26 H04R25/00

    摘要: A hearing compensation system for the hearing impaired comprises an input transducer for converting acoustical information at an input to electrical signals at an output, an output transducer for converting electrical signals at an input to acoustical information at an output, a plurality of bandpass filters, each bandpass filter having an input connected to the output of said input transducer, a plurality of AGC circuits, each individual AGC circuit associated with a different one of the bandpass filters and having an input connected to the output of its associated bandpass filter and an output connected to the input of the output transducer. The bandpass filters and AGC circuits may be divided into two processing channels, one for low frequencies and one for high frequencies and may drive separate audio transducers, one configured for maximum efficiency at low frequencies and one configured for maximum efficiency at high frequencies.

    摘要翻译: 用于听力受损的听力补偿系统包括:输入变换器,用于将输入处的声学信息转换成输出端的电信号;输出换能器,用于将输入处的电信号转换成输出处的声学信息,多个带通滤波器,每个 带通滤波器,具有连接到所述输入换能器的输出端的输入,多个AGC电路,每个单独的AGC电路与不同的带通滤波器相关联,并且具有连接到其相关带通滤波器的输出的输入端和连接的输出端 到输出传感器的输入。 带通滤波器和AGC电路可以分为两个处理通道,一个用于低频,一个用于高频,并且可以驱动单独的音频换能器,一个配置为在低频下实现最大效率,一个配置为在高频下实现最大效率。

    Digital hearing aid using differential signal representations
    2.
    发明授权
    Digital hearing aid using differential signal representations 失效
    数字助听器使用差分信号表示

    公开(公告)号:US6044162A

    公开(公告)日:2000-03-28

    申请号:US771704

    申请日:1996-12-20

    IPC分类号: H04R25/00

    CPC分类号: H04R25/356 H04R25/505

    摘要: A hearing compensation system comprises an input transducer for converting acoustical information at an input thereof to electrical signals at an output thereof, a differential analog-to-digital converter sampling the electrical signals output from the input transducer at an input thereof and outputting differential signal samples at an output thereof, a digital signal processing circuit having an input connected to the output of the differential analog-to-digital converter and operating on the differential signal samples to form processed differential signal samples at an output thereof, and an output transducer for converting electrical signals at an input thereof to acoustical information at an output thereof, the processed differential signal samples coupled to the input of the output transducer.

    摘要翻译: 听力补偿系统包括:输入变换器,用于将其输入处的声学信息转换成其输出端的电信号,差分模数转换器对输入的输入端输出的电信号进行采样,并输出差分信号采样 在其输出端具有数字信号处理电路,其输入端连接到差分模数转换器的输出端并对差分信号采样进行操作,以在其输出端形成经处理的差分信号采样,以及输出转换器,用于转换 其输入端的电信号到其输出处的声信息,经处理的差分信号样本耦合到输出换能器的输入端。

    Method for storing and retrieving digital image data from an imaging array
    3.
    发明授权
    Method for storing and retrieving digital image data from an imaging array 有权
    用于从成像阵列存储和检索数字图像数据的方法

    公开(公告)号:US06731397B1

    公开(公告)日:2004-05-04

    申请号:US09316731

    申请日:1999-05-21

    IPC分类号: G06K100

    摘要: A method for storing digital information from an image sensor comprises the steps of providing an image sensor producing three-color output data at each of a plurality of pixel locations; providing a digital storage device coupled to the image sensor; sensing three-color digital output data from the image sensor; and storing said three-color output data as digital data in the digital storage device without performing any interpolation on the three-color output data. The data may be compressed prior to storage and expanded after retrieval from storage. In a preferred embodiment, the image sensor comprises a triple-junction active pixel sensor array.

    摘要翻译: 一种用于从图像传感器存储数字信息的方法包括以下步骤:在多个像素位置的每一个处提供产生三色输出数据的图像传感器; 提供耦合到所述图像传感器的数字存储设备; 从图像传感器感测三色数字输出数据; 并将所述三色输出数据作为数字数据存储在数字存储装置中,而不对三色输出数据进行任何插值。 数据可以在存储之前被压缩,并在从存储器检索之后被扩展。 在优选实施例中,图像传感器包括三结有源像素传感器阵列。

    pMOS EEPROM non-volatile data storage
    4.
    发明授权
    pMOS EEPROM non-volatile data storage 有权
    pMOS EEPROM非易失性数据存储

    公开(公告)号:US6144581A

    公开(公告)日:2000-11-07

    申请号:US201327

    申请日:1998-11-30

    IPC分类号: G11C16/04

    CPC分类号: G11C16/0416 G11C16/10

    摘要: A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.

    摘要翻译: pMOS EEPROM单元包括源极,漏极,通道,控制栅极和阱接触。 该器件是一个功能齐全的单元件p型浮栅MOSFET。 浮动栅极与阱接触重叠,并完全围绕漏极和源植入。 通过热电子注入将pMOS单元写入,使用内在反馈机制来写入模拟值。 通过在晶体管漏极处的空穴冲击电离在通道中产生热电子。 Fowler-Nordheim隧道消除了pMOS细胞。 隧道电压仅施加到阱以从浮动栅极隧道电子。 井源井漏井路口通过护环免受破坏。

    Three-terminal silicon synaptic device
    5.
    发明授权
    Three-terminal silicon synaptic device 失效
    三端硅突触装置

    公开(公告)号:US5825063A

    公开(公告)日:1998-10-20

    申请号:US690198

    申请日:1996-07-26

    IPC分类号: G11C27/00 H01L29/788

    CPC分类号: G11C27/005 H01L29/7885

    摘要: A three-terminal silicon MOS transistor with a time-varying transfer function is provided which may operate both as a single transistor analog learning device and as a single transistor non-volatile analog memory. The time-varying transfer function is achieved by adding or removing electrons from the fully insulated floating gate of an N-type MOS floating gate transistor. The transistor has a control gate capacitively coupled to the floating gate; it is from the perspective of this control gate that the transfer function of the transistor is modified. Electrons are removed from the floating gate via Fowler-Nordheim tunneling. Electrons are added to the floating gate via hot-electron injection.

    摘要翻译: 提供具有时变传递函数的三端硅MOS晶体管,其可以同时作为单晶体管模拟学习装置和单晶体管非易失性模拟存储器工作。 通过从N型MOS浮栅晶体管的完全绝缘的浮栅中添加或去除电子来实现时变传递函数。 晶体管具有电容耦合到浮动栅极的控制栅极; 从该控制栅极的角度看,晶体管的传递函数被修改。 电子通过Fowler-Nordheim隧道从浮动门去除。 电子通过热电子注入添加到浮动栅极。

    Paintbrush stylus for capacitive touch sensor pad
    6.
    发明授权
    Paintbrush stylus for capacitive touch sensor pad 失效
    用于电容式触摸传感器垫的画笔触控笔

    公开(公告)号:US5488204A

    公开(公告)日:1996-01-30

    申请号:US324438

    申请日:1994-10-17

    摘要: A proximity sensor system includes a touch-sensor pad with a sensor matrix array having a characteristic capacitance on horizontal and vertical conductors connected to sensor pads. The capacitance changes as a function of the proximity of an object or objects to the sensor matrix. The change in capacitance of each node in both the X and Y directions of the matrix due to the approach of an object is converted to a set of voltages in the X and Y directions. These voltages are processed by circuitry to develop electrical signals representative of the centroid of the profile of the object, i.e, its position in the X and Y dimensions. Noise reduction and background level setting techniques inherently available in the architecture are employed. A conductive paintbrush-type stylus is used to produce paint-like strokes on a display associated with the touch-sensor pad.

    摘要翻译: 接近传感器系统包括具有传感器矩阵阵列的触摸传感器焊盘,该传感器阵列在连接到传感器焊盘的水平和垂直导体上具有特征电容。 电容根据物体或传感器矩阵的接近度而变化。 由于物体的接近,矩阵的X和Y方向上的每个节点的电容的变化被转换成在X和Y方向上的一组电压。 这些电压由电路处理以产生表示物体轮廓的质心的电信号,即其在X和Y尺寸中的位置。 采用本构架中固有可用的降噪和背景设置技术。 导电画笔型触笔用于在与触摸传感器垫相关联的显示器上产生油漆状笔触。

    Writable analog reference voltage storage device
    7.
    发明授权
    Writable analog reference voltage storage device 失效
    可写模拟参考电压存储器件

    公开(公告)号:US5166562A

    公开(公告)日:1992-11-24

    申请号:US697410

    申请日:1991-05-09

    摘要: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.

    摘要翻译: 用于产生用于参考或偏置使用的N个模拟电压信号的电路使用N个模拟浮动栅极存储装置。 提供电子注入电路用于将电子注入到上面,并且提供隧道结构用于从每个浮动栅极存储装置的浮动栅极去除电子。 跟随放大器连接到每个浮动栅极存储装置并驱动模拟输出电压总线。 电容器连接到每个模拟输出存储总线。 每个模拟输出电压总线和公共监视器/动态负载总线之间连接一个模拟传输门。 每个模拟传输门由选通信号驱动。

    CMOS single phase registers
    8.
    发明授权
    CMOS single phase registers 失效
    CMOS单相寄存器

    公开(公告)号:US5103116A

    公开(公告)日:1992-04-07

    申请号:US685598

    申请日:1991-04-15

    IPC分类号: H03K3/356

    CPC分类号: H03K3/35606 H03K3/356156

    摘要: A CMOS single phase register includes two pairs of cross coupled CMOS inverters connected together by transistor switches. The first pair of cross-coupled CMOS inverters is connected to a complementary pair of data inputs through a first pair of transistor switches which turn on in response to a first logic level. The complementary outputs of the first pair of cross-coupled CMOS inverters is connected to the inputs of the second pair of cross-coupled CMOS inverters through a second pair of transistor switches which turn on in response to a second logic level. The complementary outputs of the CMOS single phase register of the present invention are the outputs of the second pair of cross-coupled CMOS inverters. The ground connections of the first pair of cross-coupled CMOS inverters is made through a transistor switch which turns on in response to the first logic level. The positive voltage supply connections of the second pair of cross-coupled CMOS inverters is made through a transistor switch which turns on in response to the second logic level. A single clock line is connected to the gates of all of the transistor switches.

    摘要翻译: CMOS单相寄存器包括由晶体管开关连接在一起的两对交叉耦合CMOS反相器。 第一对交叉耦合CMOS反相器通过响应于第一逻辑电平而导通的第一对晶体管开关连接到互补数据输入对。 第一对交叉耦合CMOS反相器的互补输出通过响应于第二逻辑电平而导通的第二对晶体管开关连接到第二对交叉耦合CMOS反相器的输入。 本发明的CMOS单相寄存器的互补输出是第二对交叉耦合CMOS反相器的输出。 第一对交叉耦合CMOS反相器的接地连接通过晶体管开关来实现,晶体管开关响应于第一逻辑电平而导通。 第二对交叉耦合CMOS反相器对的正电压供应连接通过晶体管开关来实现,晶体管开关响应于第二逻辑电平而导通。 单个时钟线连接到所有晶体管开关的栅极。

    Winner-take-all circuits for neural computing systems
    9.
    发明授权
    Winner-take-all circuits for neural computing systems 失效
    用于神经计算系统的获胜者电路

    公开(公告)号:US5059814A

    公开(公告)日:1991-10-22

    申请号:US277795

    申请日:1988-11-30

    IPC分类号: G06N3/063

    CPC分类号: G06N3/063 G06N3/0635

    摘要: A CMOS analog integrated circuit comprising a plurality of nodes for simultaneously computing the largest of the signals at inputs of the nodes. There is a common line supplying current and producing a maximum voltage potential and a plurality of nodes connected to the common line. Each node comprises a follower transistor having a source operably connected to the common line for sourcing current and a gate being the input of the node and being connected to a current signal input source providing a current signal to the node to be compared to the current signals at respective ones of the other nodes. There is an inhibitor transistor having a gate connected to the common line and a drain operably connected to the gate of the follower transistor. The inhibitor transistor provides the voltage output of the node and inhibits the voltage output at all nodes connected to the common line which have a current signal which is smaller than the largest current signal connected to one of the nodes. A plurality of non-linear resistors may be disposed in the common line between respective ones of the nodes of limit current flow therebetween and thereby form subgroups having a single "winner" with each subgroup. A slope limiting transistor may be diode-connected in series with the inhibitor transistor to limit the slope of the voltage output from the inhibitor transistor.

    摘要翻译: 一种CMOS模拟集成电路,包括多个节点,用于在节点的输入处同时计算最大的信号。 存在供给电流并产生最大电压电位的公共线和连接到公共线的多个节点。 每个节点包括跟随器晶体管,其具有可操作地连接到公共线的源,用于提取电流,栅极是节点的输入,并且连接到电流信号输入源,该电流信号输入源向节点提供电流信号以与电流信号进行比较 在其他节点的各个节点。 存在具有连接到公共线的栅极的抑制晶体管和可操作地连接到跟随器晶体管的栅极的漏极。 抑制晶体管提供节点的电压输出,并且禁止连接到公共线的所有节点处的电压输出,其具有小于连接到节点之一的最大电流信号的电流信号。 多个非线性电阻器可以设置在它们之间的极限电流流动的相应节点之间的公共线中,从而形成具有每个子组的单个“赢家”的子组。 斜率限制晶体管可以与抑制晶体管串联二极管,以限制从抑制晶体管输出的电压的斜率。

    Subthreshold CMOS amplifier with offset adaptation
    10.
    发明授权
    Subthreshold CMOS amplifier with offset adaptation 失效
    具有偏移适应的亚阈值CMOS放大器

    公开(公告)号:US4935702A

    公开(公告)日:1990-06-19

    申请号:US282176

    申请日:1988-12-09

    摘要: An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage.

    摘要翻译: 具有随机输入偏移电压的集成电路放大器是可适应的,使得可以抵消输入偏移电压。 输入节点是浮动输入节点,并且通过第一电容器耦合到输入信号源。 第二电容器连接在放大器的输出端和浮动节点之间。 第二电容器上方的紫外线窗口允许通过施加紫外线将浮动节点充电到有效地抵消输入偏移电压的电压。