公开(公告)号：US10217644B2

公开(公告)日：2019-02-26

申请号：US13556217

申请日：2012-07-24

申请人： Thomas Grille ,  Ursula Hedenig ,  Joern Plagmann ,  Helmut Schoenherr ,  Ralph Muth

发明人： Thomas Grille ,  Ursula Hedenig ,  Joern Plagmann ,  Helmut Schoenherr ,  Ralph Muth

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00

摘要： In various aspects of the disclosure, a semiconductor device including at least one semiconductor die; a dielectric layer adjoining the semiconductor die; geometric structures formed in the dielectric layer; and a conductive layer deposited over the dielectric layer, wherein the conductive layer is at least partially located over the geometric structures.

公开(公告)号：US20140027915A1

公开(公告)日：2014-01-30

申请号：US13556217

申请日：2012-07-24

申请人： Thomas GRILLE ,  Ursula Hedenig ,  Joern Plagmann ,  Helmut Schoenherr ,  Ralph Muth

发明人： Thomas GRILLE ,  Ursula Hedenig ,  Joern Plagmann ,  Helmut Schoenherr ,  Ralph Muth

IPC分类号： H01L23/498 ,  H01L21/283

CPC分类号： H01L21/31111 ,  H01L21/31116 ,  H01L21/76822 ,  H01L23/3142 ,  H01L23/3192 ,  H01L24/05 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

摘要： In various aspects of the disclosure, a semiconductor device including at least one semiconductor die; a dielectric layer adjoining the semiconductor die; geometric structures formed in the dielectric layer; and a conductive layer deposited over the dielectric layer, wherein the conductive layer is at least partially located over the geometric structures.

摘要翻译： 在本公开的各个方面中，包括至少一个半导体管芯的半导体器件; 邻接半导体管芯的电介质层; 电介质层中形成的几何结构; 以及沉积在所述介电层上的导电层，其中所述导电层至少部分地位于所述几何结构之上。