公开(公告)号：US10217644B2

公开(公告)日：2019-02-26

申请号：US13556217

申请日：2012-07-24

申请人： Thomas Grille ,  Ursula Hedenig ,  Joern Plagmann ,  Helmut Schoenherr ,  Ralph Muth

发明人： Thomas Grille ,  Ursula Hedenig ,  Joern Plagmann ,  Helmut Schoenherr ,  Ralph Muth

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00

摘要： In various aspects of the disclosure, a semiconductor device including at least one semiconductor die; a dielectric layer adjoining the semiconductor die; geometric structures formed in the dielectric layer; and a conductive layer deposited over the dielectric layer, wherein the conductive layer is at least partially located over the geometric structures.

公开(公告)号：US20140027915A1

公开(公告)日：2014-01-30

申请号：US13556217

申请日：2012-07-24

申请人： Thomas GRILLE ,  Ursula Hedenig ,  Joern Plagmann ,  Helmut Schoenherr ,  Ralph Muth

发明人： Thomas GRILLE ,  Ursula Hedenig ,  Joern Plagmann ,  Helmut Schoenherr ,  Ralph Muth

IPC分类号： H01L23/498 ,  H01L21/283

CPC分类号： H01L21/31111 ,  H01L21/31116 ,  H01L21/76822 ,  H01L23/3142 ,  H01L23/3192 ,  H01L24/05 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

摘要： In various aspects of the disclosure, a semiconductor device including at least one semiconductor die; a dielectric layer adjoining the semiconductor die; geometric structures formed in the dielectric layer; and a conductive layer deposited over the dielectric layer, wherein the conductive layer is at least partially located over the geometric structures.

摘要翻译： 在本公开的各个方面中，包括至少一个半导体管芯的半导体器件; 邻接半导体管芯的电介质层; 电介质层中形成的几何结构; 以及沉积在所述介电层上的导电层，其中所述导电层至少部分地位于所述几何结构之上。

公开(公告)号：US08871550B2

公开(公告)日：2014-10-28

申请号：US13480295

申请日：2012-05-24

申请人： Thomas Grille ,  Ursula Hedenig ,  Martin Zgaga ,  Daniel Maurer

发明人： Thomas Grille ,  Ursula Hedenig ,  Martin Zgaga ,  Daniel Maurer

IPC分类号： H01L21/00 ,  H01L29/84 ,  H01L21/306

CPC分类号： H01L21/30608 ,  B81C1/00619 ,  B81C2201/0125 ,  H04R19/005

摘要： A method for processing a wafer having microelectromechanical system structures at the first main surface includes applying a masking material at the second main surface and structuring the masking material to obtain a plurality of masked areas and a plurality of unmasked areas at the second main surface. The method further includes anisotropically etching the wafer from the second main surface at the unmasked areas to form a plurality of recesses. The masking material is then removed at least at some of the masked areas to obtain previously masked areas. The method further includes anisotropically etching the wafer from the second main surface at the unmasked areas and the previously masked areas to increase a depth of the recesses and reduce a thickness of the wafer at the previously masked areas.

摘要翻译： 一种用于在第一主表面处理具有微机电系统结构的晶片的方法包括在第二主表面处施加掩模材料并构造掩模材料，以在第二主表面处获得多个掩模区域和多个未掩模区域。 该方法还包括在未掩蔽区域从第二主表面各向异性地蚀刻晶片以形成多个凹部。 至少在一些掩蔽区域处去除掩模材料以获得先前掩蔽的区域。 该方法还包括在未掩蔽区域和先前掩蔽的区域从第二主表面各向异性地蚀刻晶片，以增加凹槽的深度并减小先前掩蔽区域的晶片厚度。

公开(公告)号：US20140061677A1

公开(公告)日：2014-03-06

申请号：US13598841

申请日：2012-08-30

申请人： Bernhard Jakoby ,  Ventsislav Lachiev ,  Thomas Grille ,  Peter Irsigler ,  Sokratis Sgouridis ,  Ursula Hedenig ,  Thomas Krotscheck Ostermann

发明人： Bernhard Jakoby ,  Ventsislav Lachiev ,  Thomas Grille ,  Peter Irsigler ,  Sokratis Sgouridis ,  Ursula Hedenig ,  Thomas Krotscheck Ostermann

IPC分类号： H01L33/48

CPC分类号： G01N21/552 ,  G01N21/648 ,  G01N21/7703 ,  G01N21/7746

摘要： Some embodiments of the present disclosure relate to an infrared (IR) opto-electronic sensor having a silicon waveguide implemented on a single silicon integrated chip. The IR sensor has a semiconductor substrate having a silicon waveguide extends along a length between a radiation input conduit and a radiation output conduit. The radiation input conduit couples radiation into the silicon waveguide, while the radiation output conduit couples radiation out from the silicon waveguide. The silicon waveguide conveys the IR radiation from the radiation input conduit to the radiation output conduit at a single mode. As the radiation is conveyed by the silicon waveguide, an evanescent field is formed that extends outward from the silicon waveguide to interact with a sample positioned between the radiation input conduit and the radiation output conduit.

摘要翻译： 本公开的一些实施例涉及具有在单个硅集成芯片上实现的硅波导的红外（IR）光电传感器。 IR传感器具有半导体衬底，其具有沿着辐射输入导管和辐射输出导管之间的长度延伸的硅波导。 辐射输入导管将辐射耦合到硅波导中，而辐射输出导管将辐射从硅波导耦合出来。 硅波导以单一模式将来自辐射输入导管的IR辐射传送到辐射输出导管。 当辐射由硅波导传送时，形成从硅波导向外延伸的消逝场，以与位于辐射输入导管和辐射输出导管之间的样品相互作用。

公开(公告)号：US09417186B2

公开(公告)日：2016-08-16

申请号：US13598841

申请日：2012-08-30

申请人： Bernhard Jakoby ,  Ventsislav Lachiev ,  Thomas Grille ,  Peter Irsigler ,  Ursula Hedenig ,  Sokratis Sgouridis ,  Thomas Krotscheck Ostermann

发明人： Bernhard Jakoby ,  Ventsislav Lachiev ,  Thomas Grille ,  Peter Irsigler ,  Ursula Hedenig ,  Sokratis Sgouridis ,  Thomas Krotscheck Ostermann

IPC分类号： H01L33/48 ,  G01N21/552 ,  G01N21/64 ,  G01N21/77

CPC分类号： G01N21/552 ,  G01N21/648 ,  G01N21/7703 ,  G01N21/7746

摘要： Some embodiments of the present disclosure relate to an infrared (IR) opto-electronic sensor having a silicon waveguide implemented on a single silicon integrated chip. The IR sensor has a semiconductor substrate having a silicon waveguide extends along a length between a radiation input conduit and a radiation output conduit. The radiation input conduit couples radiation into the silicon waveguide, while the radiation output conduit couples radiation out from the silicon waveguide. The silicon waveguide conveys the IR radiation from the radiation input conduit to the radiation output conduit at a single mode. As the radiation is conveyed by the silicon waveguide, an evanescent field is formed that extends outward from the silicon waveguide to interact with a sample positioned between the radiation input conduit and the radiation output conduit.

摘要翻译： 本公开的一些实施例涉及具有在单个硅集成芯片上实现的硅波导的红外（IR）光电传感器。 IR传感器具有半导体衬底，其具有沿着辐射输入导管和辐射输出导管之间的长度延伸的硅波导。 辐射输入导管将辐射耦合到硅波导中，而辐射输出导管将辐射从硅波导耦合出来。 硅波导以单一模式将来自辐射输入导管的IR辐射传送到辐射输出导管。 当辐射由硅波导传送时，形成从硅波导向外延伸的消逝场，以与位于辐射输入导管和辐射输出导管之间的样品相互作用。

公开(公告)号：US20130313661A1

公开(公告)日：2013-11-28

申请号：US13480295

申请日：2012-05-24

申请人： Thomas Grille ,  Ursula Hedenig ,  Martin Zgaga ,  Daniel Maurer

发明人： Thomas Grille ,  Ursula Hedenig ,  Martin Zgaga ,  Daniel Maurer

IPC分类号： H01L21/306 ,  H01L29/84

CPC分类号： H01L21/30608 ,  B81C1/00619 ,  B81C2201/0125 ,  H04R19/005

摘要： A method for processing a wafer having microelectromechanical system structures at the first main surface includes applying a masking material at the second main surface and structuring the masking material to obtain a plurality of masked areas and a plurality of unmasked areas at the second main surface. The method further includes anisotropically etching the wafer from the second main surface at the unmasked areas to form a plurality of recesses. The masking material is then removed at least at some of the masked areas to obtain previously masked areas. The method further includes anisotropically etching the wafer from the second main surface at the unmasked areas and the previously masked areas to increase a depth of the recesses and reduce a thickness of the wafer at the previously masked areas.

摘要翻译： 一种用于在第一主表面处理具有微机电系统结构的晶片的方法包括在第二主表面处施加掩模材料并构造掩模材料，以在第二主表面处获得多个掩模区域和多个未掩模区域。 该方法还包括在未掩蔽区域从第二主表面各向异性地蚀刻晶片以形成多个凹部。 至少在一些掩蔽区域处去除掩模材料以获得先前掩蔽的区域。 该方法还包括在未掩蔽区域和先前掩蔽的区域从第二主表面各向异性地蚀刻晶片，以增加凹槽的深度并减小先前掩蔽区域的晶片厚度。