-
1.发明申请System and Computer Program Product for Dynamically Managing Power in MicroProcessor Chips According to Present Processing Demands 有权根据当前处理要求，微处理器芯片动态管理系统和计算机程序产品公开(公告)号：US20080229128A1
公开(公告)日：2008-09-18
申请号：US12131507
申请日：2008-06-02
IPC分类号： G06F1/00
CPC分类号： G06F1/32 , G06F1/3203 , G06F1/3287 , G06F9/30101 , G06F9/3885 , Y02D10/171 , Y02D50/20
摘要： A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.
摘要翻译： 公开了一种方法，系统和计算机程序产品，用于在包括微处理器芯片内的物理硬件元件的微处理器芯片中动态管理电力。 选择执行一个进程。 然后识别执行该过程所需的硬件元素。 微处理器芯片中的电源通过改变被识别为必要的硬件元件的当前功率状态来动态地改变。
-
2.发明授权Method for dynamically managing power in microprocessor chips according to present processing demands 有权根据当前处理需求动态管理微处理器芯片功率的方法公开(公告)号：US07401240B2
公开(公告)日：2008-07-15
申请号：US10860407
申请日：2004-06-03
CPC分类号： G06F1/32 , G06F1/3203 , G06F1/3287 , G06F9/30101 , G06F9/3885 , Y02D10/171 , Y02D50/20
摘要： A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.
摘要翻译： 公开了一种方法，系统和计算机程序产品，用于在包括微处理器芯片内的物理硬件元件的微处理器芯片中动态管理电力。 选择执行一个进程。 然后识别执行该过程所需的硬件元素。 微处理器芯片中的电源通过改变被识别为必要的硬件元件的当前功率状态来动态地改变。
-
公开(公告)号：US08028290B2
公开(公告)日：2011-09-27
申请号：US11468547
申请日：2006-08-30
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.
摘要翻译： 在为多个指令集架构（ISA）需要多重支持的虚拟机环境中提供功率高效灵活的平台的系统中支持多指令集架构。 处理器包括具有不同的本机ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。 虚拟机管理程序控制核心的操作，定位核心，并在必要时启用实例化具有指定ISA的虚拟机的请求。 ISA可以由特定的操作系统和/或应用程序要求来指定。
-
4.发明申请公开(公告)号：US20110271079A1
公开(公告)日：2011-11-03
申请号：US13182181
申请日：2011-07-13
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.
摘要翻译： 支持多指令集架构的多核处理器为需要多个支持多指令集体系结构（ISAs）的虚拟机环境提供功率高效且灵活的平台。 处理器包括具有不同的本地ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。 多个核心可以共享公共的第一级高速缓存并且被互斥地选择用于操作，或者可以提供多个一级缓存，一个与每个核心和根据需要运行的核心相关联，包括同时执行不同的ISA。 虚拟机管理程序控制核心的操作并定位核心，并且如果需要，当接收到具有指定的ISA的虚拟机的实例化请求时，它可以启用它。
-
公开(公告)号：US08806182B2
公开(公告)日：2014-08-12
申请号：US13182181
申请日：2011-07-13
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.
摘要翻译： 支持多指令集架构的多核处理器为需要多个支持多指令集体系结构（ISAs）的虚拟机环境提供功率高效且灵活的平台。 处理器包括具有不同的本地ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。 多个核心可以共享公共的第一级高速缓存并且被互斥地选择用于操作，或者可以提供多个一级缓存，一个与每个核心和根据需要运行的核心相关联，包括同时执行不同的ISA。 虚拟机管理程序控制核心的操作并定位核心，并且如果需要，当接收到具有指定的ISA的虚拟机的实例化请求时，它可以启用它。
-
6.发明申请公开(公告)号：US20080059769A1
公开(公告)日：2008-03-06
申请号：US11468547
申请日：2006-08-30
IPC分类号： G06F9/40
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.
摘要翻译： 支持多指令集架构的多核处理器为需要多个支持多指令集体系结构（ISAs）的虚拟机环境提供功率高效且灵活的平台。 处理器包括具有不同的本地ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。 多个核心可以共享公共的第一级高速缓存并且被互斥地选择用于操作，或者可以提供多个一级缓存，一个与每个核心和根据需要运行的核心相关联，包括同时执行不同的ISA。 虚拟机管理程序控制核心的操作并定位核心，并且如果需要，当接收到具有指定的ISA的虚拟机的实例化请求时，它可以启用它。
-
7.发明授权公开(公告)号：US07949008B2
公开(公告)日：2011-05-24
申请号：US11342952
申请日：2006-01-30
申请人： William Joseph Armstrong , Richard Louis Arndt , Renato J. Recio , James Walter Rymarczyk , Jacobo A. Vargas
发明人： William Joseph Armstrong , Richard Louis Arndt , Renato J. Recio , James Walter Rymarczyk , Jacobo A. Vargas
IPC分类号： H04J3/16
CPC分类号： G06F21/53 , H04M1/66 , H04M1/72558 , H04M1/72561 , H04W88/02
摘要： An audio application program is isolated from an Internet application program in a cell phone system having a processor. An operating system program, a partition manager process and the audio and Internet application programs are stored in a computer readable memory of the cell phone. The method includes executing the partition manager process, the audio application program and the Internet application program by the cell phone system processor. Executing the partition manager process includes the partition manager process controlling the audio application program executing to be associated with a first executing instance of the cell phone operating system and the Internet application program executing to be associated with a second executing instance of the cell phone operating system, so that the audio application program is isolated from the Internet application program.
摘要翻译： 音频应用程序与具有处理器的蜂窝电话系统中的因特网应用程序隔离。 操作系统程序，分区管理器处理和音频和因特网应用程序存储在蜂窝电话的计算机可读存储器中。 该方法包括由手机系统处理器执行分区管理器处理，音频应用程序和因特网应用程序。 执行分区管理器处理包括分配管理器进程，其控制执行与蜂窝电话操作系统的第一执行实例相关联的音频应用程序和执行为与手机操作系统的第二执行实例相关联的因特网应用程序 ，使得音频应用程序与互联网应用程序隔离。
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.021 秒)
