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    Processing methods of forming a capacitor
    1.
    发明授权
    Processing methods of forming a capacitor 失效
    形成电容器的处理方法

    公开(公告)号：US6146961A

    公开(公告)日：2000-11-14

    申请号：US880356

    申请日：1997-06-23

    申请人： Thomas M. Graettinger ,  Paul J. Schuele ,  Pierre C. Fazan ,  Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh ,  Thomas Arthur Figura

    发明人： Thomas M. Graettinger ,  Paul J. Schuele ,  Pierre C. Fazan ,  Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh ,  Thomas Arthur Figura

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/84

    摘要： Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void. In another aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure only partially filling in the void to provide a tubular structure.

    摘要翻译： 描述形成电容器的电容器和方法。 根据一个实施方案，在衬底节点位置上形成电容器开口。 随后在电容器开口内形成导电材料，并与节点位置进行电连接。 在电容器开口内形成突出的绝缘结构，并且包括一个侧面外表面，其外表面的至少一部分由邻近的导电材料支撑并向下垂直延伸。 第一和第二电容器板及其之间的电介质层形成在电容器开口内并由突出结构支撑。 在一个方面，导电材料被形成为占据小于全部电容器开口并且在其中留下空隙，其中突起结构基本上如果不是完全填充在空隙中。 另一方面，导电材料被形成为占据小于全部电容器开口并且在其中留下空隙，其中突出结构仅部分地填充在空隙中以提供管状结构。

    Processing methods of forming a capacitor, and capacitor construction
    3.
    发明授权
    Processing methods of forming a capacitor, and capacitor construction 有权
    形成电容器和电容器结构的加工方法

    公开(公告)号：US06580114B1

    公开(公告)日：2003-06-17

    申请号：US09497935

    申请日：2000-02-04

    申请人： Thomas M Graettinger ,  Paul J. Schuele ,  Pierre C. Fazan ,  Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh ,  Thomas Arthur Figura

    发明人： Thomas M Graettinger ,  Paul J. Schuele ,  Pierre C. Fazan ,  Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh ,  Thomas Arthur Figura

    IPC分类号： H01L27108

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/84

    摘要： Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void. In another aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure only partially filling in the void to provide a tubular structure.

    摘要翻译： 描述形成电容器的电容器和方法。 根据一个实施方案，在衬底节点位置上形成电容器开口。 随后在电容器开口内形成导电材料，并与节点位置进行电连接。 在电容器开口内形成突出的绝缘结构，并且包括一个侧面外表面，其外表面的至少一部分由邻近的导电材料支撑并向下垂直延伸。 第一和第二电容器板及其之间的电介质层形成在电容器开口内并由突出结构支撑。 在一个方面，导电材料被形成为占据小于全部电容器开口并且在其中留下空隙，其中突起结构基本上如果不是完全填充在空隙中。 另一方面，导电材料被形成为占据小于全部电容器开口并且在其中留下空隙，其中突出结构仅部分地填充在空隙中以提供管状结构。

    Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug
    4.
    发明授权
    Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug 失效
    制造在铂层和多晶硅插塞之间具有复合阻挡层的接触结构的方法

    公开(公告)号：US6093615A

    公开(公告)日：2000-07-25

    申请号：US290655

    申请日：1994-08-15

    申请人： Paul J. Schuele ,  Pierre C. Fazan

    发明人： Paul J. Schuele ,  Pierre C. Fazan

    IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L21/20

    CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002

    摘要： This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer. The barrier layer process begins by etching the upper surface of the polysilicon plug using a selective polysilicon etch until it is recessed at least 1000 .ANG. below the upper surface of the thick dielectric layer. Using a collimated sputter source, a titanium layer having a thickness of 100-500 .ANG. is deposited over the surface of the in-process wafer, thus covering the upper surfaces of the polysilicon plugs. A layer of amorphous titanium carbonitride having a thickness of 100-300 .ANG. is then deposited via low-pressure chemical vapor deposition. This is followed by the deposition of a reactively sputtered titanium nitride layer having a thickness of 1000-2000 .ANG.. The wafer is then planarized to remove the titanium, titanium carbonitride and titanium nitride, except that which is in the recesses on top of the silicon plugs. The wafer is then annealed in nitrogen to react the titanium layer with the silicon on the upper surfaces of the plugs to form titanium silicide. A platinum layer is then deposited and patterned to form lower capacitor electrodes which are electrically coupled to the polysilicon plugs through the titanium silicide, titanium nitride and titanium carbonitride layers.

    摘要翻译： 本发明是一种在制造在硅晶片上的动态随机存取存储器中形成厚电介质层形成的多晶硅插塞的上表面和铂下电容器板之间形成有效的氮化钛阻挡层的工艺。 阻挡层工艺通过使用选择性多晶硅蚀刻蚀刻多晶硅插塞的上表面开始，直到其在厚电介质层的上表面下方至少凹入1000个ANGSTROM。 使用准直的溅射源，在工作晶片的表面上沉积厚度为100-500的钛层，从而覆盖多晶硅插塞的上表面。 然后通过低压化学气相沉积沉积厚度为100-300安培的无定形碳氮化钛层。 随后沉积厚度为1000-2000安培的反应溅射的氮化钛层。 然后将晶片平坦化以除去钛，碳氮化钛和氮化钛，除了位于硅插头顶部的凹槽中。 然后将晶片在氮气中退火以使钛层与插塞的上表面上的硅反应形成硅化钛。 然后沉积铂层并图案化以形成较低电容器电极，其通过硅化钛，氮化钛和碳氮化钛层电耦合到多晶硅插塞。

    Sputter and CVD deposited titanium nitride barrier layer between a platinum layer and a polysilicon plug
    6.
    发明授权
    Sputter and CVD deposited titanium nitride barrier layer between a platinum layer and a polysilicon plug 失效
    接触结构在铂层和多晶硅插塞之间具有复合阻挡层堆叠

    公开(公告)号：US5717250A

    公开(公告)日：1998-02-10

    申请号：US614798

    申请日：1996-03-07

    申请人： Paul J. Schuele ,  Pierre C. Fazan

    发明人： Paul J. Schuele ,  Pierre C. Fazan

    IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002

    摘要： This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer. The barrier layer process begins by etching the upper surface of the polysilicon plug using a selective polysilicon etch until it is recessed at least 1000 .ANG. below the upper surface of the thick dielectric layer. Using a collimated sputter source, a titanium layer having a thickness of 100-500 .ANG. is deposited over the surface of the in-process wafer, thus covering the upper surfaces of the polysilicon plugs. A layer of amorphous titanium carbonitride having a thickness of 100-300 .ANG. is then deposited via low-pressure chemical vapor deposition. This is followed by the deposition of a reactively sputtered titanium nitride layer having a thickness of 1000-2000 .ANG.. The wafer is then planarized to remove the titanium, titanium carbonitride and titanium nitride, except that which is in the recesses on top of the silicon plugs. The wafer is then annealed in nitrogen to react the titanium layer with the silicon on the upper surfaces of the plugs to form titanium silicide. A platinum layer is then deposited and patterned to form lower capacitor electrodes which are electrically coupled to the polysilicon plugs through the titanium silicide, titanium nitride and titanium carbonitride layers.

    摘要翻译： 本发明是一种在制造在硅晶片上的动态随机存取存储器中形成厚电介质层形成的多晶硅插塞的上表面和铂下电容器板之间形成有效的氮化钛阻挡层的工艺。 阻挡层工艺通过使用选择性多晶硅蚀刻蚀刻多晶硅插塞的上表面开始，直到其在厚电介质层的上表面下方至少凹入1000个ANGSTROM。 使用准直的溅射源，在工作晶片的表面上沉积厚度为100-500的钛层，从而覆盖多晶硅插塞的上表面。 然后通过低压化学气相沉积沉积厚度为100-300安培的无定形碳氮化钛层。 随后沉积厚度为1000-2000安培的反应溅射的氮化钛层。 然后将晶片平坦化以除去钛，碳氮化钛和氮化钛，除了位于硅插头顶部的凹槽中。 然后将晶片在氮气中退火以使钛层与插塞的上表面上的硅反应形成硅化钛。 然后沉积铂层并图案化以形成较低电容器电极，其通过硅化钛，氮化钛和碳氮化钛层与多晶硅插塞电耦合。

    Method of Forming a Thin Film Transistor
    9.
    发明申请
    Method of Forming a Thin Film Transistor 审中-公开
    形成薄膜晶体管的方法

    公开(公告)号：US20110024762A1

    公开(公告)日：2011-02-03

    申请号：US12901981

    申请日：2010-10-11

    申请人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

    发明人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

    IPC分类号： H01L29/66

    CPC分类号： H01L29/78678 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78672 ,  H01L29/78675

    摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

    摘要翻译： 相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。 薄膜晶体管可以被制造为底部门控或顶部门控。 可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。 优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与 多晶薄膜层。

    Integrated circuitry for semiconductor memory
    10.
    发明授权
    Integrated circuitry for semiconductor memory 失效
    半导体存储器的集成电路

    公开(公告)号：US07705383B2

    公开(公告)日：2010-04-27

    申请号：US08530661

    申请日：1995-09-20

    申请人： Brent Keeth ,  Pierre C. Fazan

    发明人： Brent Keeth ,  Pierre C. Fazan

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10888 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10811

    摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells, more preferably, at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.

    摘要翻译： 公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。 半导体存储器件包括i）总共不超过68,000,000个功能和可操作地寻址的存储器单元，布置在形成在半导体管芯上的多个存储器阵列中; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域， 功能和可操作寻址的存储器单元，更优选至少100平方微米的具有至少170个功能和可操作寻址的存储单元的连续管芯表面区域。