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公开(公告)号：US20080080226A1
公开(公告)日：2008-04-03
申请号：US11526850
申请日：2006-09-25
申请人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
发明人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
CPC分类号： G11C11/5614 , G11C7/1006 , G11C7/22 , G11C11/16 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2207/107 , G11C2211/5641
摘要： A memory system includes a plurality of resistive memory cell fields including at least a first resistive memory cell field and a second resistive memory cell field, the first resistive memory cell field formed with a plurality of resistive memory cells storing data at a first data storage speed, the second resistive memory cell field formed with a plurality of resistive memory cells storing data at a second data storage speed lower than the first data storage speed, and a controller controlling data transfer between the plurality of resistive memory cell fields.
摘要翻译： 存储器系统包括多个电阻存储单元区域，至少包括第一电阻存储单元区域和第二电阻存储单元区域，第一电阻存储单元区域形成有多个电阻存储单元，以第一数据存储速度存储数据 形成有以低于第一数据存储速度的第二数据存储速度存储数据的多个电阻性存储单元形成的第二电阻性存储单元区域，以及控制器，用于控制多个电阻性存储单元区域之间的数据传输。
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2.发明申请Memory cell arrangements and methods of manufacturing memory cell arrangements 有权存储单元布置和制造存储单元布置的方法公开(公告)号：US20080073694A1
公开(公告)日：2008-03-27
申请号：US11526149
申请日：2006-09-22
申请人： Josef Willer , Thomas Mikolajick , Nicolas Nagel , Michael Specht
发明人： Josef Willer , Thomas Mikolajick , Nicolas Nagel , Michael Specht
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.
摘要翻译： 存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管 晶体管，其中至少有一些是存储单元。 电介质材料在第一存储单元串和第二存储单元串之间和之上。 源极/漏极线沟槽限定在电介质材料中。 源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。 导电填充材料设置在源极/漏极线槽中。 电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。
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公开(公告)号：US07838921B2
公开(公告)日：2010-11-23
申请号：US11526149
申请日：2006-09-22
申请人： Josef Willer , Thomas Mikolajick , Nicolas Nagel , Michael Specht
发明人： Josef Willer , Thomas Mikolajick , Nicolas Nagel , Michael Specht
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.
摘要翻译： 存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管 晶体管，其中至少有一些是存储单元。 电介质材料在第一存储单元串和第二存储单元串之间和之上。 源极/漏极线沟槽限定在电介质材料中。 源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。 导电填充材料设置在源极/漏极线槽中。 电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。
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4.发明申请Semiconductor memory device and method of operating a semiconductor memory device 审中-公开半导体存储器件和操作半导体存储器件的方法公开(公告)号：US20070231991A1
公开(公告)日：2007-10-04
申请号：US11396398
申请日：2006-03-31
IPC分类号： H01L21/8238
CPC分类号： H01L29/792 , G11C16/0475 , G11C16/14 , G11C16/16
摘要： A semiconductor memory device includes a channel region, a gate electrode adjacent the channel region, and a charge-trapping layer between the channel region and the gate electrode. A voltage is applied between the gate electrode and the channel region to cause a first current of a first kind of charge carriers from the channel region to move into the charge-trapping layer and to cause a second current of a second kind of charge carriers from the gate electrode to move into the charge-trapping layer, until the value of the second current is at least half the amount of the first current value.
摘要翻译： 半导体存储器件包括沟道区，与沟道区相邻的栅电极以及沟道区和栅电极之间的电荷俘获层。 在栅极电极和沟道区域之间施加电压，使来自沟道区域的第一种电荷载流子的第一电流移动到电荷俘获层中，并引起第二种载流子的第二电流 栅电极移动到电荷捕获层中，直到第二电流的值至少为第一电流值的一半。
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公开(公告)号：US07714377B2
公开(公告)日：2010-05-11
申请号：US11737617
申请日：2007-04-19
IPC分类号： H01L29/788
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , Y10T29/49117
摘要： Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.
摘要翻译： 本发明的实施例涉及具有存储单元布置的集成电路及其制造方法。 在本发明的一个实施例中，集成电路具有存储单元布置，其包括沿其纵向方向延伸的翅片结构作为第一方向，包括第一绝缘层，设置在第一绝缘层上方的第一有源区，第二绝缘层 设置在所述第一有源区上方的第二有源区，设置在所述第二绝缘层上方的第二有源区，电荷存储层结构，其至少布置在所述鳍结构的至少一个侧壁上，覆盖所述第一有源区的至少一部分，并且至少 第二有源区的一部分，以及设置在电荷存储层结构旁边的控制栅。
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公开(公告)号：US20080259687A1
公开(公告)日：2008-10-23
申请号：US11737617
申请日：2007-04-19
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , Y10T29/49117
摘要： Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.
摘要翻译： 本发明的实施例涉及具有存储单元布置的集成电路及其制造方法。 在本发明的一个实施例中，集成电路具有存储单元布置，其包括沿其纵向方向延伸的翅片结构作为第一方向，包括第一绝缘层，设置在第一绝缘层上方的第一有源区，第二绝缘层 设置在所述第一有源区上方的第二有源区，设置在所述第二绝缘层上方的第二有源区，电荷存储层结构，其至少布置在所述鳍结构的至少一个侧壁上，覆盖所述第一有源区的至少一部分，并且至少 第二有源区的一部分，以及设置在电荷存储层结构旁边的控制栅。
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公开(公告)号：US20060245233A1
公开(公告)日：2006-11-02
申请号：US11119376
申请日：2005-04-29
申请人： Thomas Mikolajick , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Josef Willer , Corvin Liaw
IPC分类号： G11C17/00
CPC分类号： G11C16/0483 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.
摘要翻译： 一个电荷捕获多位存储单元的阵列被布置在虚拟地NAND架构中。 存储器单元被Fowler-Nordheim擦除，将电子隧穿到存储器层中。 写入操作通过热空穴注入来实现。 写入电压通过位线施加到两个串联的NAND链。 要编程的存储器单元侧的后续位线保持浮置电位，而另一侧的位线被设置为禁止电压，该禁止电压被提供以阻止寻址的存储器单元的程序干扰 被编程。 电荷俘获存储器单元的虚拟NAND架构能够提高存储密度。
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8.发明申请Semiconductor memory having charge trapping memory cells and fabrication method thereof 有权具有电荷捕获存储单元的半导体存储器及其制造方法公开(公告)号：US20060192266A1
公开(公告)日：2006-08-31
申请号：US11067983
申请日：2005-02-28
IPC分类号： H01L29/00
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42336 , H01L29/7923
摘要： A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
摘要翻译： 一种具有电荷捕获存储单元的半导体存储器，其中存储晶体管的每个沟道区域的电流方向相对于相关字线横向延伸，位线被布置在字线的顶侧，并且以某种方式 存在与源极 - 漏极区电气绝缘的导电局部互连件，其在字线之间的间隔中以部分布置并以与后者的电绝缘方式并且连接到位线的方式布置，其中栅极电极 布置在至少部分地形成在存储器基板中的沟槽中。
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9.发明授权Semiconductor memory having charge trapping memory cells and fabrication method thereof 失效具有电荷捕获存储单元的半导体存储器及其制造方法公开(公告)号：US07662687B2
公开(公告)日：2010-02-16
申请号：US12110849
申请日：2008-04-28
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42336 , H01L29/7923
摘要： A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
摘要翻译： 一种具有电荷捕获存储单元的半导体存储器及其制造方法。 存储晶体管的每个通道区域的电流流动方向相对于相关字线横向延伸，位线布置在字线的顶侧，并以与之相隔离的方式布置，并且导电的局部 存在源极 - 漏极区域的互连，其在字线之间的间隔中以部分布置并且以与后者的电绝缘并且连接到位线的方式布置，其中栅极电极布置在至少部分地形成在存储器中的沟槽中 基质。
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公开(公告)号：US20070082446A1
公开(公告)日：2007-04-12
申请号：US11246908
申请日：2005-10-07
IPC分类号： H01L21/336 , H01L21/76 , H01L21/302 , H01L21/461
CPC分类号： H01L27/115 , H01L21/76897 , H01L27/11568
摘要： A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.
摘要翻译： 提供了用于制造堆叠的非易失性存储单元的方法。 提供具有形成埋入位线的多个扩散区域的半导体晶片。 电荷捕获层和导电层沉积在半导体晶片的表面上。 在导电层的顶部使用掩模层，形成绝缘层的接触孔。 蚀刻停止层沉积在半导体晶片的表面上。 在蚀刻停止层上方，沉积介电层并图案化以形成接触孔。 随后，接触孔通过蚀刻停止层和绝缘层扩大到埋入位线。
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