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    Memory cell arrangements and methods of manufacturing memory cell arrangements
    1.
    发明申请
    Memory cell arrangements and methods of manufacturing memory cell arrangements 有权
    存储单元布置和制造存储单元布置的方法

    公开(公告)号：US20080073694A1

    公开(公告)日：2008-03-27

    申请号：US11526149

    申请日：2006-09-22

    申请人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    发明人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    IPC分类号： H01L29/788

    CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

    摘要翻译： 存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管 晶体管，其中至少有一些是存储单元。 电介质材料在第一存储单元串和第二存储单元串之间和之上。 源极/漏极线沟槽限定在电介质材料中。 源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。 导电填充材料设置在源极/漏极线槽中。 电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。

    Memory cell arrangements
    2.
    发明授权
    Memory cell arrangements 有权
    存储单元布置

    公开(公告)号：US07838921B2

    公开(公告)日：2010-11-23

    申请号：US11526149

    申请日：2006-09-22

    申请人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    发明人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    IPC分类号： H01L29/788

    CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

    摘要翻译： 存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管 晶体管，其中至少有一些是存储单元。 电介质材料在第一存储单元串和第二存储单元串之间和之上。 源极/漏极线沟槽限定在电介质材料中。 源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。 导电填充材料设置在源极/漏极线槽中。 电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。

    Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module
    4.
    发明申请
    Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module 审中-公开
    集成电路，电池，电池布置，集成电路的制造方法，电池的制造方法，存储器模块

    公开(公告)号：US20080237694A1

    公开(公告)日：2008-10-02

    申请号：US11728960

    申请日：2007-03-27

    申请人： Michael Specht ,  Nicolas Nagel ,  Josef Willer

    发明人： Michael Specht ,  Nicolas Nagel ,  Josef Willer

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L29/513

    摘要： The invention relates to integrated circuits, to a cell, to a cell arrangement, to a method for manufacturing an integrated circuit, to a method for manufacturing a cell, and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a cell, the cell including a low-k dielectric layer, a first high-k dielectric layer disposed above the low-k dielectric layer, a charge trapping layer disposed above the first high-k dielectric layer, and a second high-k dielectric layer disposed above the charge trapping layer.

    摘要翻译： 本发明涉及集成电路，单元，单元布置，集成电路的制造方法，单元的制造方法以及存储器模块。 在本发明的实施例中，提供了具有单元的集成电路，该单元包括低k电介质层，设置在低k电介质层上方的第一高k电介质层，设置在第一 高k电介质层和设置在电荷捕获层上方的第二高k电介质层。

    Memory array having an interconnect and method of manufacture
    5.
    发明申请
    Memory array having an interconnect and method of manufacture 审中-公开
    具有互连和制造方法的存储器阵列

    公开(公告)号：US20080074927A1

    公开(公告)日：2008-03-27

    申请号：US11525547

    申请日：2006-09-22

    申请人： Franz Hofmann ,  Michael Specht ,  Nicolas Nagel ,  Josef Willer

    发明人： Franz Hofmann ,  Michael Specht ,  Nicolas Nagel ,  Josef Willer

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A memory array includes first, second, third and forth memory cell strings. Each of the first, second, third, and fourth memory cell strings includes a number of serially-coupled memory cells, including a first memory cell and a last memory cell. A first interconnect is coupled to a first bit line and to each of the first, second, third and fourth memory cell strings. The first interconnect includes first, second, third and fourth string input select gates. Each input select gate has a first terminal coupled to the first bit line, and a second terminal coupled to one of the respective first, second, third or fourth memory cell strings.

    摘要翻译： 存储器阵列包括第一，第二，第三和第四存储器单元串。 第一，第二，第三和第四存储器单元串中的每一个包括多个串行耦合的存储器单元，包括第一存储单元和最后存储单元。 第一互连耦合到第一位线和第一，第二，第三和第四存储器单元串中的每一个。 第一互连包括第一，第二，第三和第四串输入选择门。 每个输入选择栅极具有耦合到第一位线的第一端子和耦合到相应的第一，第二，第三或第四存储器单元串之一的第二端子。

    Integrated circuits and methods of manufacturing thereof
    6.
    发明授权
    Integrated circuits and methods of manufacturing thereof 有权
    集成电路及其制造方法

    公开(公告)号：US07714377B2

    公开(公告)日：2010-05-11

    申请号：US11737617

    申请日：2007-04-19

    申请人： Michael Specht ,  Nicolas Nagel ,  Franz Hofmann ,  Thomas Mikolajick

    发明人： Michael Specht ,  Nicolas Nagel ,  Franz Hofmann ,  Thomas Mikolajick

    IPC分类号： H01L29/788

    CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  Y10T29/49117

    摘要： Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.

    摘要翻译： 本发明的实施例涉及具有存储单元布置的集成电路及其制造方法。 在本发明的一个实施例中，集成电路具有存储单元布置，其包括沿其纵向方向延伸的翅片结构作为第一方向，包括第一绝缘层，设置在第一绝缘层上方的第一有源区，第二绝缘层 设置在所述第一有源区上方的第二有源区，设置在所述第二绝缘层上方的第二有源区，电荷存储层结构，其至少布置在所述鳍结构的至少一个侧壁上，覆盖所述第一有源区的至少一部分，并且至少 第二有源区的一部分，以及设置在电荷存储层结构旁边的控制栅。

    Integrated Circuits and Methods of Manufacturing Thereof
    7.
    发明申请
    Integrated Circuits and Methods of Manufacturing Thereof 有权
    集成电路及其制造方法

    公开(公告)号：US20080259687A1

    公开(公告)日：2008-10-23

    申请号：US11737617

    申请日：2007-04-19

    申请人： Michael Specht ,  Nicolas Nagel ,  Franz Hofmann ,  Thomas Mikolajick

    发明人： Michael Specht ,  Nicolas Nagel ,  Franz Hofmann ,  Thomas Mikolajick

    IPC分类号： G11C5/00 ,  H01R43/00

    CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  Y10T29/49117

    摘要： Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.

    摘要翻译： 本发明的实施例涉及具有存储单元布置的集成电路及其制造方法。 在本发明的一个实施例中，集成电路具有存储单元布置，其包括沿其纵向方向延伸的翅片结构作为第一方向，包括第一绝缘层，设置在第一绝缘层上方的第一有源区，第二绝缘层 设置在所述第一有源区上方的第二有源区，设置在所述第二绝缘层上方的第二有源区，电荷存储层结构，其至少布置在所述鳍结构的至少一个侧壁上，覆盖所述第一有源区的至少一部分，并且至少 第二有源区的一部分，以及设置在电荷存储层结构旁边的控制栅。

    INTEGRATED CIRCUIT INCLUDING A FIRST GATE STACK AND A SECOND GATE STACK AND A METHOD OF MANUFACTURING
    8.
    发明申请
    INTEGRATED CIRCUIT INCLUDING A FIRST GATE STACK AND A SECOND GATE STACK AND A METHOD OF MANUFACTURING 有权
    集成电路，包括第一栅极堆叠和第二栅极堆叠及其制造方法

    公开(公告)号：US20090072274A1

    公开(公告)日：2009-03-19

    申请号：US11855695

    申请日：2007-09-14

    申请人： Roman Knoefler ,  Michael Specht ,  Josef Willer

    发明人： Roman Knoefler ,  Michael Specht ,  Josef Willer

    IPC分类号： H01L27/10 ,  H01L21/8238

    CPC分类号： H01L27/11568 ,  H01L21/823828 ,  H01L27/105 ,  H01L27/11573

    摘要： An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.

    摘要翻译： 公开了一种包括第一栅极堆叠和第二栅极堆叠的集成电路及其制造方法。 一个实施例提供包括在半导体衬底的主表面的第一表面部分上的第一栅极堆叠和栅极电介质的非易失性存储器单元，以及包括在第二表面部分上的存储层堆叠的第二栅极堆叠。 将第一图案转移到第一栅极堆叠中，将第二图案转移到第二栅极堆叠中。