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    Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices
    1.
    发明授权
    Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices 有权
    使用间隔物补偿植入物损伤并减少闪存装置中的横向扩散的方法和系统

    公开(公告)号：US06410956B1

    公开(公告)日：2002-06-25

    申请号：US09478864

    申请日：2000-01-07

    申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

    发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

    IPC分类号： H01L2976

    CPC分类号： H01L29/66825

    摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

    摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。 至少一个栅极堆叠具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。 在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入 存放 至少一个栅极堆叠具有边缘。 所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。 在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个 在间隔物沉积之后在半导体中的漏极注入。 至少一个门具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

    Selective erasure of a non-volatile memory cell of a flash memory device
    4.
    发明授权
    Selective erasure of a non-volatile memory cell of a flash memory device 有权
    闪存设备的非易失性存储单元的选择性擦除

    公开(公告)号：US06366501B1

    公开(公告)日：2002-04-02

    申请号：US09686686

    申请日：2000-10-11

    申请人： Timothy J. Thurgate ,  Daniel Sobek

    发明人： Timothy J. Thurgate ,  Daniel Sobek

    IPC分类号： G11C1134

    CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/14

    摘要： A method of selectively erasing an individual memory cell of an array of non-volatile memory cells by providing an array of non-volatile memory cells that includes a first non-volatile memory cell that is connected in series with a second non-volatile memory cell and erasing the first non-volatile memory cell while not erasing the second non-volatile memory cell.

    摘要翻译： 一种通过提供包括与第二非易失性存储器单元串联连接的第一非易失性存储器单元的非易失性存储器单元的阵列来选择性地擦除非易失性存储单元阵列的单独存储单元的方法， 以及擦除所述第一非易失性存储单元而不擦除所述第二非易失性存储单元。

    Method of programming a non-volatile memory cell using a substrate bias
    5.
    发明授权
    Method of programming a non-volatile memory cell using a substrate bias 有权
    使用衬底偏置来编程非易失性存储单元的方法

    公开(公告)号：US06456536B1

    公开(公告)日：2002-09-24

    申请号：US09884409

    申请日：2001-06-19

    申请人： Daniel Sobek ,  Timothy J. Thurgate ,  Janet Wang ,  Narbeh Derhacobian

    发明人： Daniel Sobek ,  Timothy J. Thurgate ,  Janet Wang ,  Narbeh Derhacobian

    IPC分类号： G11C1604

    CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/12

    摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.

    摘要翻译： 一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。 该方法包括在栅极上施加恒定的第一电压，在第一区域上施加第二恒定电压，并向衬底施加恒定和负的第三电压，使得当与第三区域相比时，溢出电子的效应显着降低 不存在恒定电压。

    Method for laterally peaked source doping profiles for better erase control in flash memory devices
    6.
    发明授权
    Method for laterally peaked source doping profiles for better erase control in flash memory devices 失效
    用于横向峰值源掺杂分布的方法，用于在闪速存储器件中更好的擦除控制

    公开(公告)号：US06329257B1

    公开(公告)日：2001-12-11

    申请号：US08994140

    申请日：1997-12-19

    申请人： Scott D. Luning ,  Daniel Sobek ,  Timothy J. Thurgate

    发明人： Scott D. Luning ,  Daniel Sobek ,  Timothy J. Thurgate

    IPC分类号： H01L21336

    CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/36 ,  H01L29/7883

    摘要： A system and method for controlling a characteristic of at least one memory cell on a semiconductor is disclosed. The at least one memory cell includes a gate stack, a source, and a drain. The semiconductor includes a surface. In one aspect, the method and system include providing the gate stack on the semiconductor and providing the source including a source dopant having a local peak in concentration. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor. In another aspect the method and system includes a memory cell on a semiconductor. The semiconductor includes a surface. The memory cell includes a gate stack on the semiconductor, a source, and a drain. The gate stack has a first edge and a second edge. The source is located in proximity to the first edge of the gate stack. The drain is located in proximity to the second edge of the gate stack. A first portion of the source is disposed under the gate stack. The source includes a source dopant having a local peak in concentration of the source dopant. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor.

    摘要翻译： 公开了一种用于控制半导体上的至少一个存储单元的特性的系统和方法。 所述至少一个存储单元包括栅极堆叠，源极和漏极。 半导体包括表面。 在一个方面，所述方法和系统包括在半导体上提供栅极堆叠并且提供源，其包括具有局部峰浓度的源掺杂剂。 源掺杂剂的局部峰浓度位于栅极堆叠之下并且靠近半导体表面的一部分。 在另一方面，该方法和系统包括半导体上的存储单元。 半导体包括表面。 存储单元包括半导体上的栅极堆叠，源极和漏极。 栅极堆叠具有第一边缘和第二边缘。 源极位于栅堆叠的第一边缘附近。 漏极位于栅堆叠的第二边缘附近。 源极的第一部分设置在栅极堆叠下方。 该源包括源掺杂剂，其具有源掺杂剂浓度的局部峰。 源掺杂剂的局部峰浓度位于栅极堆叠之下并且靠近半导体表面的一部分。

    Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects
    7.
    发明授权
    Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects 失效
    用于形成减少带对隧道电流和短沟道效应的半导体器件的方法

    公开(公告)号：US6153487A

    公开(公告)日：2000-11-28

    申请号：US40107

    申请日：1998-03-17

    申请人： Scott D. Luning ,  Timothy J. Thurgate ,  Daniel Sobek ,  Nicholas H. Tripsas

    发明人： Scott D. Luning ,  Timothy J. Thurgate ,  Daniel Sobek ,  Nicholas H. Tripsas

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/22 ,  H01L21/38 ,  H01L29/76

    CPC分类号： H01L29/66825 ,  H01L21/2652

    摘要： The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

    摘要翻译： 本发明提供一种用于形成半导体器件的方法和系统，其减少带间隧穿电流和短沟道效应。 该方法和系统包括将第一低剂量砷注入到衬底中的区域中，通过衬底的一部分热扩散第一低剂量砷，将第二较高剂量的砷注入到衬底的区域中， 第二高剂量砷进入底物区域。 在本发明中，第一和第二砷植入物的组合具有梯度横向轮廓，其降低带对隧道电流和短通道效应。 该方法还提高了半导体器件的可靠性和性能。

    Method of programming a non-volatile memory cell using a vertical electric field
    8.
    发明授权
    Method of programming a non-volatile memory cell using a vertical electric field 有权
    使用垂直电场对非易失性存储单元进行编程的方法

    公开(公告)号：US06487121B1

    公开(公告)日：2002-11-26

    申请号：US09899721

    申请日：2001-07-05

    申请人： Timothy J. Thurgate ,  Carl R. Huster

    发明人： Timothy J. Thurgate ,  Carl R. Huster

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475

    摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a lateral electric field within the channel that generates a depletion layer that has electrons at a bottom portion of the depletion layer and applying a vertical electric field within the channel that has a sufficient strength so that the electrons at the bottom portion of the depletion layer are injected into the charge trapping region.

    摘要翻译： 一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。 该方法包括在通道内施加横向电场，该横向电场产生在耗尽层的底部具有电子的耗尽层，并且在通道内施加具有足够强度的垂直电场，使得底部的电子 耗尽层被注入到电荷捕获区域中。

    Process for reduction of capacitance of a bitline for a non-volatile memory cell
    9.
    发明授权
    Process for reduction of capacitance of a bitline for a non-volatile memory cell 有权
    降低非易失性存储单元的位线电容的工艺

    公开(公告)号：US06417081B1

    公开(公告)日：2002-07-09

    申请号：US09721066

    申请日：2000-11-22

    申请人： Timothy J. Thurgate

    发明人： Timothy J. Thurgate

    IPC分类号： H01L21425

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A process for forming an array of memory cells that includes forming a buried bitline region by implanting an n-type dopant in a region of a semiconductor substrate, wherein there is a severe differential change going from the bitline region to the substrate region causing the capacitance of a junction between the bitline region and the semiconductor to be large and reducing the capacitance of the junction.

    摘要翻译： 一种用于形成存储单元阵列的工艺，其包括通过在半导体衬底的区域中注入n型掺杂剂来形成掩埋位线区域，其中存在从位线区域到衬底区域的严重差分变化，从而导致电容 的位线区域和半导体之间的结点较大并且减小了结的电容。

    Method and system for providing localized gate edge rounding with minimal encroachment and gate edge lifting
    10.
    发明授权
    Method and system for providing localized gate edge rounding with minimal encroachment and gate edge lifting 失效
    用于以最小的侵入和门边缘提升提供局部门边缘四舍五入的方法和系统

    公开(公告)号：US06387755B1

    公开(公告)日：2002-05-14

    申请号：US08992616

    申请日：1997-12-17

    申请人： Timothy J. Thurgate ,  Scott D. Luning

    发明人： Timothy J. Thurgate ,  Scott D. Luning

    IPC分类号： H01L21336

    CPC分类号： H01L29/66825

    摘要： A system and method for providing a memory cell on a semiconductor is disclosed. The method and system include providing an oxide layer on the semiconductor and providing at least one gate stack disposed above the oxide layer. The at least one gate stack has a corner contacting the oxide layer. The method and system further include exposing at least the corner of the at least one gate stack and rounding at least the corner of the at least one gate stack.

    摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 该方法和系统包括在半导体上提供氧化物层并提供设置在氧化物层上方的至少一个栅极堆叠。 至少一个栅极堆叠具有与氧化物层接触的拐角。 所述方法和系统还包括至少暴露所述至少一个栅极堆叠的角部并至少对所述至少一个栅极叠层的角进行舍入。