公开(公告)号：US06410956B1

公开(公告)日：2002-06-25

申请号：US09478864

申请日：2000-01-07

申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC分类号： H01L2976

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。 至少一个栅极堆叠具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。 在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入 存放 至少一个栅极堆叠具有边缘。 所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。 在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个 在间隔物沉积之后在半导体中的漏极注入。 至少一个门具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

公开(公告)号：US6025240A

公开(公告)日：2000-02-15

申请号：US993600

申请日：1997-12-18

申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

公开(公告)号：US6103602A

公开(公告)日：2000-08-15

申请号：US992618

申请日：1997-12-17

申请人： Timothy J. Thurgate ,  Vei-Han Chan

发明人： Timothy J. Thurgate ,  Vei-Han Chan

IPC分类号： H01L21/8238

CPC分类号： H01L29/7881 ,  H01L29/0847 ,  H01L29/66825 ,  H01L21/823412

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. The memory cell has a source and a drain. The method and system include providing a source implant in the semiconductor, providing a pocket implant in the semiconductor, and providing a drain implant in the semiconductor after the pocket implant is provided. Thus, short channel effects are reduced.

摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 存储单元具有源极和漏极。 该方法和系统包括在半导体中提供源植入物，在半导体中提供凹穴注入，以及在提供口袋植入物之后在半导体中提供漏极注入。 因此，短通道效应降低。

公开(公告)号：US06366501B1

公开(公告)日：2002-04-02

申请号：US09686686

申请日：2000-10-11

申请人： Timothy J. Thurgate ,  Daniel Sobek

发明人： Timothy J. Thurgate ,  Daniel Sobek

IPC分类号： G11C1134

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/14

摘要： A method of selectively erasing an individual memory cell of an array of non-volatile memory cells by providing an array of non-volatile memory cells that includes a first non-volatile memory cell that is connected in series with a second non-volatile memory cell and erasing the first non-volatile memory cell while not erasing the second non-volatile memory cell.

摘要翻译： 一种通过提供包括与第二非易失性存储器单元串联连接的第一非易失性存储器单元的非易失性存储器单元的阵列来选择性地擦除非易失性存储单元阵列的单独存储单元的方法， 以及擦除所述第一非易失性存储单元而不擦除所述第二非易失性存储单元。

公开(公告)号：US07125763B1

公开(公告)日：2006-10-24

申请号：US09885426

申请日：2001-06-19

申请人： Daniel Sobek ,  Timothy J. Thurgate ,  Mark W. Randolph

发明人： Daniel Sobek ,  Timothy J. Thurgate ,  Mark W. Randolph

IPC分类号： H01L21/8238

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： A process of fabricating a memory cell that includes a substrate that has a first region and a second region with a channel therebetween by forming a gate above the channel of the substrate, forming a bitline and siliciding the bitline.

摘要翻译： 一种制造存储单元的方法，该存储单元包括具有第一区域和第二区域的衬底，所述第一区域和第二区域之间具有通道，通过在衬底的沟道上形成栅极，形成位线并硅化位线。

公开(公告)号：US06487121B1

公开(公告)日：2002-11-26

申请号：US09899721

申请日：2001-07-05

申请人： Timothy J. Thurgate ,  Carl R. Huster

发明人： Timothy J. Thurgate ,  Carl R. Huster

IPC分类号： G11C1604

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475

摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a lateral electric field within the channel that generates a depletion layer that has electrons at a bottom portion of the depletion layer and applying a vertical electric field within the channel that has a sufficient strength so that the electrons at the bottom portion of the depletion layer are injected into the charge trapping region.

摘要翻译： 一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。 该方法包括在通道内施加横向电场，该横向电场产生在耗尽层的底部具有电子的耗尽层，并且在通道内施加具有足够强度的垂直电场，使得底部的电子 耗尽层被注入到电荷捕获区域中。

公开(公告)号：US06417081B1

公开(公告)日：2002-07-09

申请号：US09721066

申请日：2000-11-22

申请人： Timothy J. Thurgate

发明人： Timothy J. Thurgate

IPC分类号： H01L21425

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A process for forming an array of memory cells that includes forming a buried bitline region by implanting an n-type dopant in a region of a semiconductor substrate, wherein there is a severe differential change going from the bitline region to the substrate region causing the capacitance of a junction between the bitline region and the semiconductor to be large and reducing the capacitance of the junction.

摘要翻译： 一种用于形成存储单元阵列的工艺，其包括通过在半导体衬底的区域中注入n型掺杂剂来形成掩埋位线区域，其中存在从位线区域到衬底区域的严重差分变化，从而导致电容 的位线区域和半导体之间的结点较大并且减小了结的电容。

公开(公告)号：US06387755B1

公开(公告)日：2002-05-14

申请号：US08992616

申请日：1997-12-17

申请人： Timothy J. Thurgate ,  Scott D. Luning

发明人： Timothy J. Thurgate ,  Scott D. Luning

IPC分类号： H01L21336

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. The method and system include providing an oxide layer on the semiconductor and providing at least one gate stack disposed above the oxide layer. The at least one gate stack has a corner contacting the oxide layer. The method and system further include exposing at least the corner of the at least one gate stack and rounding at least the corner of the at least one gate stack.

摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 该方法和系统包括在半导体上提供氧化物层并提供设置在氧化物层上方的至少一个栅极堆叠。 至少一个栅极堆叠具有与氧化物层接触的拐角。 所述方法和系统还包括至少暴露所述至少一个栅极堆叠的角部并至少对所述至少一个栅极叠层的角进行舍入。

公开(公告)号：US06349062B1

公开(公告)日：2002-02-19

申请号：US09686693

申请日：2000-10-11

申请人： Timothy J. Thurgate

发明人： Timothy J. Thurgate

IPC分类号： G11C1134

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/14

摘要： A method of selectively erasing a bit of an individual memory cell of an array of non-volatile memory cells by providing an array of non-volatile memory cells that include a first non-volatile two bit memory cell that is connected in series with a second non-volatile memory cell. The method includes erasing a first bit of the first non-volatile two bit memory cell while not erasing a second bit of the first non-volatile memory cell.

摘要翻译： 一种通过提供非易失性存储器单元的阵列来选择性地擦除非易失性存储器单元阵列的单独存储单元的位的方法，所述非易失性存储器单元包括与第二非易失性存储器单元串联连接的第一非易失性双位存储器单元 非易失性存储单元。 该方法包括擦除第一非易失性双位存储单元的第一位而不擦除第一非易失性存储单元的第二位。

公开(公告)号：US06456536B1

公开(公告)日：2002-09-24

申请号：US09884409

申请日：2001-06-19

申请人： Daniel Sobek ,  Timothy J. Thurgate ,  Janet Wang ,  Narbeh Derhacobian

发明人： Daniel Sobek ,  Timothy J. Thurgate ,  Janet Wang ,  Narbeh Derhacobian

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/12

摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.

摘要翻译： 一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。 该方法包括在栅极上施加恒定的第一电压，在第一区域上施加第二恒定电压，并向衬底施加恒定和负的第三电压，使得当与第三区域相比时，溢出电子的效应显着降低 不存在恒定电压。