公开(公告)号：US6103602A

公开(公告)日：2000-08-15

申请号：US992618

申请日：1997-12-17

申请人： Timothy J. Thurgate ,  Vei-Han Chan

发明人： Timothy J. Thurgate ,  Vei-Han Chan

IPC分类号： H01L21/8238

CPC分类号： H01L29/7881 ,  H01L29/0847 ,  H01L29/66825 ,  H01L21/823412

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. The memory cell has a source and a drain. The method and system include providing a source implant in the semiconductor, providing a pocket implant in the semiconductor, and providing a drain implant in the semiconductor after the pocket implant is provided. Thus, short channel effects are reduced.

摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 存储单元具有源极和漏极。 该方法和系统包括在半导体中提供源植入物，在半导体中提供凹穴注入，以及在提供口袋植入物之后在半导体中提供漏极注入。 因此，短通道效应降低。

公开(公告)号：US6025240A

公开(公告)日：2000-02-15

申请号：US993600

申请日：1997-12-18

申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

公开(公告)号：US06410956B1

公开(公告)日：2002-06-25

申请号：US09478864

申请日：2000-01-07

申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC分类号： H01L2976

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。 至少一个栅极堆叠具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。 在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入 存放 至少一个栅极堆叠具有边缘。 所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。 在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个 在间隔物沉积之后在半导体中的漏极注入。 至少一个门具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

公开(公告)号：US07696018B2

公开(公告)日：2010-04-13

申请号：US12116911

申请日：2008-05-07

申请人： Antonietta Oliva ,  Louis Charles Kordus, II ,  Narbeh Derharcobian ,  Vei-Han Chan ,  Thomas E. Stewart, Jr.

发明人： Antonietta Oliva ,  Louis Charles Kordus, II ,  Narbeh Derharcobian ,  Vei-Han Chan ,  Thomas E. Stewart, Jr.

IPC分类号： H01L21/06 ,  H01L45/00

CPC分类号： H01L45/1683 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/126

摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，该相变材料的导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

公开(公告)号：US06674669B2

公开(公告)日：2004-01-06

申请号：US10268863

申请日：2002-10-09

申请人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

发明人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

IPC分类号： G11C1134

CPC分类号： G11C16/08 ,  G11C8/08

摘要： In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

摘要翻译： 在非易失性存储器阵列的每行中，所有存储器单元的选择栅极连接在一起，并用于选择用于存储器存取的行。 每行的控制栅极也连接在一起，并且每行的源极区域连接在一起。 此外，多行的控制栅极连接在一起，并且多行的源极区域连接在一起，但是如果两行的源极区域连接在一起，则它们的控制栅极不连接在一起。 如果两行中的一个被访问，但是两行中的另一行未被访问，则它们的控制栅极被驱动到不同的电压，从而降低在未访问行中穿透的可能性。

公开(公告)号：US06660585B1

公开(公告)日：2003-12-09

申请号：US09531787

申请日：2000-03-21

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen ,  Fu-Chang Hsu

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  G11C16/0416 ,  H01L21/28273

摘要： In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.

摘要翻译： 在本发明中，公开了一种堆叠栅极闪存单元，其在器件的漏极侧具有轻掺杂漏极（LDD），并且使用源使用热电子发生进行编程并使用Fowler-Nordheim隧道擦除浮动栅极。 通过利用LDD和使用源进行编程和擦除的单元的偏置来减少干扰条件。 作为减少热电子产生的LDD的结果，漏极的电场大大减小。 LDD还有助于在编程期间减少位线干扰条件。 通过将未选择的单元的位线预处理为Vcc，使未选择的单元中的瞬态位线干扰条件最小化。

公开(公告)号：US5856946A

公开(公告)日：1999-01-05

申请号：US831571

申请日：1997-04-09

申请人： Vei-Han Chan ,  Sameer Haddad ,  Chi Chang

发明人： Vei-Han Chan ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/12 ,  G11C16/04

CPC分类号： G11C16/12

摘要： A memory with controlled gate current injection during memory cell programming wherein programming circuitry applies a time-varying voltage to a control gate of the memory cell during a programming cycle. The time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate during the programming cycle.

摘要翻译： 在存储器单元编程期间具有受控栅极电流注入的存储器，其中编程电路在编程周期期间将时变电压施加到存储器单元的控制栅极。 在编程周期期间，随时间变化的电压产生从通道区域到浮动栅极的电子流量的基本恒定的速率。

公开(公告)号：US08639952B1

公开(公告)日：2014-01-28

申请号：US11716265

申请日：2007-03-09

申请人： Vei-Han Chan ,  Louis Charles Kordus, II

发明人： Vei-Han Chan ,  Louis Charles Kordus, II

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  H03K19/0008 ,  H03K19/1776

摘要： A programmable logic device (PLD) provides voltage identification (VID) codes to a voltage regulator module having VID capabilities. The voltage regulator module generates supply Vdd and/or body bias Vbb voltages according to a selected VID code. The value of the supply Vdd and/or body bias Vbb voltages generated and applied to the PLD determine the operating characteristics of the PLD. The VID codes can be provided and stored in various ways: by an addressable lookup table (LUT) integrated with the PLD, by a memory device in which the VID codes are transferred from an external memory. The VID codes may also be self-generated by auto-detect circuitry integrated with the PLD. The ability to select a particular VID code for each individual PLD allows the user to optimize operational characteristics of the device to satisfy power and/or performance requirements.

摘要翻译： 可编程逻辑器件（PLD）向具有VID功能的电压调节器模块提供电压识别（VID）代码。 电压调节器模块根据选定的VID代码产生电源Vdd和/或体偏置Vbb电压。 生成并施加到PLD的电源Vdd和/或体偏置Vbb电压的值确定PLD的操作特性。 可以以各种方式提供和存储VID代码：通过与PLD集成的可寻址查找表（LUT），其中VID代码从外部存储器传送的存储器件。 VID代码也可以通过与PLD集成的自动检测电路自行生成。 为每个独立PLD选择特定VID代码的能力允许用户优化设备的操作特性以满足功率和/或性能要求。

公开(公告)号：US20120182794A1

公开(公告)日：2012-07-19

申请号：US13433039

申请日：2012-03-28

申请人： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

发明人： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

IPC分类号： G11C11/00

CPC分类号： H01L45/1226 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1683 ,  H03K19/02

摘要： Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device.

摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。 结构允许应用，其中可以在两个有源端子之间产生电连接，并且使用单独的端子或端子来实现连接的控制。因此，加热器元件的电阻可以独立于两者之间的路径的电阻而增加 有源端子，允许使用较小的加热器元件，因此需要更少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

公开(公告)号：US07910429B2

公开(公告)日：2011-03-22

申请号：US10821100

申请日：2004-04-07

申请人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chunchieh Huang ,  Jin-Ho Kim ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao ,  George Kovall ,  Steven Ming Yang

发明人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chunchieh Huang ,  Jin-Ho Kim ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao ,  George Kovall ,  Steven Ming Yang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/7881

摘要： Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

摘要翻译： 通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分 材料 堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。 结果，氧化不沿着侧壁的多层高度均匀地进行。 本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。 更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为 深深地通过侧壁的已氧化层，例如氧化硅层。 结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。