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    Semiconductor slapper
    3.
    发明授权
    Semiconductor slapper 失效
    半导体slapper

    公开(公告)号：US5370054A

    公开(公告)日：1994-12-06

    申请号：US955189

    申请日：1992-10-01

    申请人： Robert Reams ,  Judith McCullen ,  Jonathan Terrell

    发明人： Robert Reams ,  Judith McCullen ,  Jonathan Terrell

    IPC分类号： F42B3/13 ,  F42C19/12

    CPC分类号： F42B3/13

    摘要： An RF-insensitive semiconductor slapper ignitor is created using a siliconubstrate having a first metallized portion centrally located on its bottom face to form a Schottky barrier diode thereon, and a second substantially smaller metallized portion centrally located on its top face to form a consumable plug. A flyer disc is disposed atop the second metallized portion and is propelled when the consumable plug vaporizes in response to the high current density associated with ignition. In various embodiments the flyer disc is either an insulating material such as plastic, or polyimide, or formed integral to a top contact metal layer.

    摘要翻译： 使用具有中心位于其底面上的第一金属化部分的硅衬底产生RF不敏感的半导体斩波器点火器，以在其上形成肖特基势垒二极管，以及第二基本上较小的金属化部分，位于其顶面上方以形成消耗性插头 。 传单盘设置在第二金属化部分的顶部，并且当消耗性塞子响应于与点火相关联的高电流密度而蒸发时被推进。 在各种实施例中，传单盘是绝缘材料，例如塑料或聚酰亚胺，或与顶部接触金属层一体形成。

    Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models
    4.
    发明申请
    Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models 有权
    基于布局的调制方法和紧凑模型中氮化物衬垫应力效应的优化

    公开(公告)号：US20070028195A1

    公开(公告)日：2007-02-01

    申请号：US11193711

    申请日：2005-07-29

    申请人： Dureseti Chidambarrao ,  Donald Jordan ,  Judith McCullen ,  David Onsongo ,  Tina Wagner ,  Richard Williams

    发明人： Dureseti Chidambarrao ,  Donald Jordan ,  Judith McCullen ,  David Onsongo ,  Tina Wagner ,  Richard Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

    摘要： System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).

    摘要翻译： 用于紧凑模型算法的系统和方法来准确地解释半导体器件中氮化物衬垫应力的布局引起的变化的影响。 布局敏感的压缩模型算法通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。 特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。 算法还适用于使具有单个应力衬垫膜和双应力衬垫（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击确定。

    INTEGRATED CIRCUIT DIAGNOSING METHOD, SYSTEM, AND PROGRAM PRODUCT
    6.
    发明申请
    INTEGRATED CIRCUIT DIAGNOSING METHOD, SYSTEM, AND PROGRAM PRODUCT 失效
    集成电路诊断方法，系统和程序产品

    公开(公告)号：US20050278667A1

    公开(公告)日：2005-12-15

    申请号：US11160266

    申请日：2005-06-16

    申请人： Matt Boucher ,  John Cohn ,  Richard Dauphin ,  Mark Masters ,  Judith McCullen ,  Sarah Braasch ,  Michael Sitko

    发明人： Matt Boucher ,  John Cohn ,  Richard Dauphin ,  Mark Masters ,  Judith McCullen ,  Sarah Braasch ,  Michael Sitko

    IPC分类号： G01R31/303 ,  G06F17/50

    CPC分类号： G06F17/5081 ,  G01R31/3025 ,  G01R31/303

    摘要： The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.

    摘要翻译： 本发明提供了用于诊断集成电路的方法，系统和程序产品。 特别地，本发明为集成电路的每个相关电路层捕获一个或多个图像。 基于图像，生成组件网表。 此外，通过将分层组合规则应用于组件网表生成逻辑网表。 组件网表和/或逻辑网表可以与参考网表进行比较以诊断集成电路。 本发明还可以根据从网表确定的端口，功率和/或组件引脚连接信息，组件网络表或逻辑网表，其中组件被布置。 此外，可以以选择性地显示布线连接以辅助用户智能地布置电路部件的方式来显示原理图。