利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.023 秒)

    Deep trench capacitor and method of making same
    1.
    发明授权
    Deep trench capacitor and method of making same 失效
    深沟槽电容器及其制作方法

    公开(公告)号：US07694262B2

    公开(公告)日：2010-04-06

    申请号：US11872787

    申请日：2007-10-16

    申请人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M. Shank ,  Francis Roger White

    发明人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M. Shank ,  Francis Roger White

    IPC分类号： G06F17/50

    CPC分类号： H01L29/945 ,  H01L29/66181

    摘要： A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.

    摘要翻译： 沟槽电容器，形成沟槽电容器的方法以及沟槽电容器的设计结构。 所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

    DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME
    2.
    发明申请
    DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME 有权
    深度电容电容器及其制造方法

    公开(公告)号：US20080315274A1

    公开(公告)日：2008-12-25

    申请号：US11767616

    申请日：2007-06-25

    申请人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M. Shank ,  Francis Roger White

    发明人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M. Shank ,  Francis Roger White

    IPC分类号： H01L29/92 ,  H01L21/20

    CPC分类号： H01L29/945 ,  H01L28/40

    摘要： A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.

    摘要翻译： 沟槽电容器和形成沟槽电容器的方法。 所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

    Deep trench capacitor and method of making same
    3.
    发明授权
    Deep trench capacitor and method of making same 有权
    深沟槽电容器及其制作方法

    公开(公告)号：US07812388B2

    公开(公告)日：2010-10-12

    申请号：US11767616

    申请日：2007-06-25

    申请人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M Shank ,  Francis Roger White

    发明人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M Shank ,  Francis Roger White

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/945 ,  H01L28/40

    摘要： A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.

    摘要翻译： 沟槽电容器和形成沟槽电容器的方法。 所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

    DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME
    4.
    发明申请
    DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME 失效
    深度电容电容器及其制造方法

    公开(公告)号：US20090100388A1

    公开(公告)日：2009-04-16

    申请号：US11872787

    申请日：2007-10-16

    申请人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M. Shank ,  Francis Roger White

    发明人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M. Shank ,  Francis Roger White

    IPC分类号： G06F9/45

    CPC分类号： H01L29/945 ,  H01L29/66181

    摘要： A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.

    摘要翻译： 沟槽电容器，形成沟槽电容器的方法以及沟槽电容器的设计结构。 所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

    Differential Junction Varactor
    6.
    发明申请
    Differential Junction Varactor 失效
    差分接头变容二极管

    公开(公告)号：US20080203537A1

    公开(公告)日：2008-08-28

    申请号：US11679987

    申请日：2007-02-28

    申请人： Frederick Gustav Anderson ,  Robert Mark Rassel ,  Nicholas Theodore Schmidt ,  Xudong Wang

    发明人： Frederick Gustav Anderson ,  Robert Mark Rassel ,  Nicholas Theodore Schmidt ,  Xudong Wang

    IPC分类号： H01L29/93 ,  H01L21/20

    CPC分类号： H01L29/93 ,  H01L29/417 ,  H01L29/66174

    摘要： Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions.

    摘要翻译： 差分结变容二极管的结构和方法。 该结构包括：形成在硅衬底中的硅第一区域，第一掺杂剂类型的第一区域; 以及与所述第一区域物理和电接触的多个硅第二区域，所述多个第二区域间隔开并且彼此不物理接触，所述多个第二掺杂剂类型的第二区域不同于 第二掺杂剂类型; 电连接到第一区域的阴极端子; 电连接到所述多个第二区域中的第一组第二区域的第一阳极端子; 以及第二阳极端子，电连接到所述多个第二区域中的第二组第二硅区域，所述第一组第二区域的第二区域与所述第二组第二区域的第二区域交替。

    MIM CAPACITOR AND METHOD OF MAKING SAME
    7.
    发明申请
    MIM CAPACITOR AND METHOD OF MAKING SAME 有权
    MIM电容器及其制造方法

    公开(公告)号：US20070296085A1

    公开(公告)日：2007-12-27

    申请号：US11425549

    申请日：2006-06-21

    申请人： Douglas Duane Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel

    发明人： Douglas Duane Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel

    IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L28/60

    摘要： A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, the upper plate having a top surface, a bottom surface and sidewalls; a spreader plate comprising one or more electrically conductive layers, the spreader plate having a top surface, a bottom surface and sidewalls; and a dielectric block comprising one or more dielectric layers the dielectric block having a top surface, a bottom surface and sidewalls, the top surface of the dielectric block in physical contact with the bottom surface of the upper plate, the bottom surface of the dielectric block over the top surface of the spreader plate, the sidewalls of the upper plate and the dielectric block essentially co-planer.

    摘要翻译： 一种MIM电容器及其制造方法。 该装置包括包括一个或多个导电层的上板，上板具有顶表面，底表面和侧壁; 包括一个或多个导电层的扩展板，所述扩展板具有顶表面，底表面和侧壁; 以及介电块，其包括一个或多个电介质层，介电块具有顶表面，底表面和侧壁，介电块的顶表面与上板的底表面物理接触，介质块的底表面 在扩展板的顶表面上方，上板和介质块的侧壁基本上是共平面的。

    BICMOS DEVICES ON ETSOI
    9.
    发明申请
    BICMOS DEVICES ON ETSOI 审中-公开
    BICMOS设备在ETSOI

    公开(公告)号：US20130277753A1

    公开(公告)日：2013-10-24

    申请号：US13451806

    申请日：2012-04-20

    申请人： William F. Clark, JR. ,  Qizhi Liu ,  Robert Mark Rassel ,  Yun Shi

    发明人： William F. Clark, JR. ,  Qizhi Liu ,  Robert Mark Rassel ,  Yun Shi

    IPC分类号： H01L27/088 ,  G06F17/50 ,  H01L21/8249

    CPC分类号： H01L21/84 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/1203

    摘要： A BiCMOS device structure, method of manufacturing the same and design structure thereof are provided. The BiCMOS device structure includes a substrate having a layer of semiconductor material upon an insulating layer. The BiCMOS device structure further includes a bipolar junction transistor structure formed in a first region of the substrate having an extrinsic base layer formed at least partially from a portion of the layer of semiconductor material.

    摘要翻译： 提供BiCMOS器件结构，其制造方法及其设计结构。 BiCMOS器件结构包括在绝缘层上具有半导体材料层的衬底。 BiCMOS器件结构还包括形成在衬底的第一区域中的双极结型晶体管结构，其具有至少部分地由半导体材料层的一部分形成的非本征基极层。