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    Transferring execution from one instruction stream to another
    1.
    发明申请
    Transferring execution from one instruction stream to another 有权
    将执行从一个指令流传输到另一个指令流

    公开(公告)号：US20050086650A1

    公开(公告)日：2005-04-21

    申请号：US11003768

    申请日：2004-12-02

    申请人： John Yates ,  David Reese ,  Paul Hohensee ,  Stephen Purcell ,  Korbin Van Dyke

    发明人： John Yates ,  David Reese ,  Paul Hohensee ,  Stephen Purcell ,  Korbin Van Dyke

    IPC分类号： G06F9/455 ,  G06F9/45 ,  G06F7/38 ,  G06F9/44 ,  G06F15/00 ,  G06F15/76

    CPC分类号： G06F9/45533

    摘要： A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

    摘要翻译： 计算机具有能够执行两个指令集架构（ISA）的指令流水线电路。 二进制翻译器至少将计算机程序的选定部分从ISA的较低性能转换为ISA的更高性能的一个。 当即将执行在低性能ISA中编码的程序区域时，硬件启动查询，以确定是否存在更高性能的转换。 如果是这样，即将执行的指令被中止，并且控制转移到更高性能的转换。 执行较高性能的翻译后，在排除后的指令下游的一个点重新建立较低性能区域的执行，在逻辑上相当于在较低性能区域的代码被允许的情况下 继续。

    Systems and methods for primitive intersection in ray tracing
    2.
    发明授权
    Systems and methods for primitive intersection in ray tracing 有权
    光线跟踪中原始交点的系统和方法

    公开(公告)号：US08988433B2

    公开(公告)日：2015-03-24

    申请号：US13096585

    申请日：2011-04-28

    申请人： Stephen Purcell ,  Christopher Philip Alan Tann ,  Jason Rupert Redgrave ,  Cüneyt Özdaş

    发明人： Stephen Purcell ,  Christopher Philip Alan Tann ,  Jason Rupert Redgrave ,  Cüneyt Özdaş

    IPC分类号： G06T15/06

    CPC分类号： G06T15/06 ,  G06T15/20

    摘要： Aspects include systems, methods, and media for implementing methods relating to increasing consistency of results during intersection testing. In an example, vertexes define edges of primitives composing a scene (e.g., triangles defining a mesh for a surface of an object in a 3-D scene). An edge can be shared between two primitives. Intersection testing algorithms can use tests involving edges to determine whether or not the ray intersects a primitive defined by those edges. In one approach, a precedence among the vertexes defining a particular edge is enforced for such intersection testing. The precedence causes an intersection tester to always test a given edge in the same orientation, regardless of which primitive defined (at least in part) by that edge is being intersection tested.

    摘要翻译： 方面包括系统，方法和媒体，用于实现在交叉测试期间提高结果一致性的方法。 在一个示例中，顶点定义构成场景的图元的边缘（例如，为三维场景中的对象的表面定义网格的三角形）。 一个边可以在两个基元之间共享。 交叉测试算法可以使用涉及边缘的测试来确定光线是否与由这些边缘定义的原语相交。 在一种方法中，为这种交叉点测试强制定义特定边缘的顶点中的优先级。 优先级使交叉测试仪始终以相同的方向测试给定的边缘，而不管该边缘是否被交叉测试定义（至少部分）的原始图案。

    Isolation connector for an intravascular implantable medical device
    3.
    发明授权
    Isolation connector for an intravascular implantable medical device 有权
    用于血管内植入式医疗设备的隔离连接器

    公开(公告)号：US08204596B2

    公开(公告)日：2012-06-19

    申请号：US12263240

    申请日：2008-10-31

    申请人： Terrance Ransbury ,  Stephen Purcell

    发明人： Terrance Ransbury ,  Stephen Purcell

    IPC分类号： A61N1/00

    CPC分类号： A61N1/375

    摘要： Devices and methods providing for a isolation connector for a generally cylindrical or frustro-cylindrical housing of an implantable intravascular medical device are described herein. The isolation connector has a generally annular exterior surface, a proximal end, and a distal end. The isolation connector includes a housing interface portion at the proximal end which is secured to a first end of the housing. The proximal end of the housing interface portion is constructed to be obverse to the first end of the housing and presents a perimeter of substantially similar size and shape to the perimeter of the first end of the housing. The isolation connector further includes a first insulator portion disposed adjacent to a distal end of the housing interface portion. The isolation connector may further include a feed-through channel constructed to traverse the proximal and distal ends of the isolation connector and is defined through the housing interface portion and the first insulator portion. In an optional embodiment, an electrical conductor is disposed within the feed-through channel to electrically coupled at least one component disposed within the housing to at least one component disposed beyond the insulator portion.

    摘要翻译： 本文描述了提供用于可植入血管内医疗装置的大致圆柱形或截头圆柱形壳体的隔离连接器的装置和方法。 隔离连接器具有大致环形的外表面，近端和远端。 隔离连接器包括在近端处的壳体接口部分，其被固定到壳体的第一端。 壳体接口部分的近端被构造成朝向壳体的第一端正面，并且具有与壳体的第一端的周边基本相似的尺寸和形状的周边。 隔离连接器还包括邻近壳体接口部分的远端设置的第一绝缘体部分。 隔离连接器还可以包括构造成穿过隔离连接器的近端和远端并且通过壳体接口部分和第一绝缘体部分限定的馈通通道。 在可选实施例中，电导体设置在馈通通道内，以将布置在壳体内的至少一个部件电耦合到设置在绝缘体部分之外的至少一个部件。

    LAYERED CROSSBAR FOR INTERCONNECTION OF MULTIPLE PROCESSORS AND SHARED MEMORIES
    4.
    发明申请
    LAYERED CROSSBAR FOR INTERCONNECTION OF MULTIPLE PROCESSORS AND SHARED MEMORIES 有权
    用于互连多个处理器和共享存储器的层叠交叉

    公开(公告)号：US20070208901A1

    公开(公告)日：2007-09-06

    申请号：US11463842

    申请日：2006-08-10

    申请人： Stephen Purcell ,  Christopher Cheng

    发明人： Stephen Purcell ,  Christopher Cheng

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1657 ,  G06F13/4022 ,  G06F15/17375

    摘要： A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.

    摘要翻译： 一种方法和装置包括多个处理器组，每个处理器组具有多个处理器开关芯片，每个处理器开关芯片具有多个处理器和处理器交叉开关，每个处理器连接到处理器交叉开关; 多个开关组，每个具有多个开关交叉开关组，每个开关交叉开关组具有多个开关组，每个开关组具有多个开关交叉开关组，每个开关交叉开关组具有多个开关交叉开关，每个开关交叉连接到每个处理器组中的处理器交叉开关，其中没有两个开关 交换机组中的交叉开关连接到相同的处理器交叉开关; 具有多个存储器开关芯片的多个存储器组，每个存储器开关芯片各自具有多个存储器控制器和存储器交叉开关，每个存储器控制器连接到存储器交叉开关，每个存储器组中的每个存储器交叉开关连接到相应的所有开关交叉开关 其中一个交换机组，其中没有两个存储器组连接到相同的交换机组。

    Sliced crossbar architecture with no inter-slice communication
    5.
    发明申请
    Sliced crossbar architecture with no inter-slice communication 有权

    公开(公告)号：US20060285377A1

    公开(公告)日：2006-12-21

    申请号：US11514854

    申请日：2006-08-31

    申请人： Stephen Purcell ,  Scott Kimura

    发明人： Stephen Purcell ,  Scott Kimura

    IPC分类号： G11C21/02

    CPC分类号： G06F15/173 ,  G06F13/1647 ,  G06F13/1657 ,  H04L49/101 ,  H04L49/1523

    摘要： A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.

    ARCHITECTURES FOR CONCURRENT GRAPHICS PROCESSING OPERATIONS
    7.
    发明申请
    ARCHITECTURES FOR CONCURRENT GRAPHICS PROCESSING OPERATIONS 有权
    相关图形处理操作的架构

    公开(公告)号：US20120249553A1

    公开(公告)日：2012-10-04

    申请号：US13525300

    申请日：2012-06-16

    申请人： Luke Tilman Peterson ,  James Alexander McCombe ,  Ryan R. Salsbury ,  Stephen Purcell

    发明人： Luke Tilman Peterson ,  James Alexander McCombe ,  Ryan R. Salsbury ,  Stephen Purcell

    IPC分类号： G06T15/06 ,  G06T1/20

    CPC分类号： G06T15/06 ,  G06T15/005 ,  G06T15/50 ,  G06T15/80

    摘要： Ray tracing, and more generally, graphics operations taking place in a 3-D scene, involve a plurality of constituent graphics operations. Scheduling of graphics operations for concurrent execution on a computer may increase throughput. In aspects herein, constituent graphics operations are scheduled in groups, having members selected according to disclosed aspects. Processing for specific graphics operations in a group can be deferred if all the operations in the group cannot be further tested concurrently. Graphics operations that have been deferred are recombined into two or more different groups and ultimately complete processing, through a required number of iterations of such process. In one application, the performance of the graphics operations perform a search in which respective 1:1 matches between different types of geometric shapes involved in the 3-D scene are identified. For example, closest intersections between rays and scene geometry can be identified by processing scheduled according to disclosed aspects.

    摘要翻译： 光线跟踪，更一般地，在3-D场景中发生的图形操作涉及多个组成图形操作。 在计算机上并行执行的图形操作的调度可以增加吞吐量。 在这些方面中，组件图形操作按组进行调度，具有根据公开的方面选择的成员。 如果组中的所有操作无法进一步并发测试，则可以推迟对组中特定图形操作的处理。 已经推迟的图形操作被重新组合成两个或更多个不同的组，并且通过所需数量的这种过程的迭代最终完成处理。 在一个应用中，图形操作的性能执行搜索，其中识别在3-D场景中涉及的不同类型的几何形状之间相应的1：1匹配。 例如，可以通过根据所公开的方面调度的处理来识别光线和场景几何之间的最接近的交点。

    ARCHITECTURES FOR PARALLELIZED INTERSECTION TESTING AND SHADING FOR RAY-TRACING RENDERING
    8.
    发明申请
    ARCHITECTURES FOR PARALLELIZED INTERSECTION TESTING AND SHADING FOR RAY-TRACING RENDERING 有权
    用于平行跟踪测试和边缘渲染的架构

    公开(公告)号：US20090262132A1

    公开(公告)日：2009-10-22

    申请号：US12408478

    申请日：2009-03-20

    申请人： Luke Tilman Peterson ,  James Alexander McCombe ,  Ryan R. Salsbury ,  Stephen Purcell

    发明人： Luke Tilman Peterson ,  James Alexander McCombe ,  Ryan R. Salsbury ,  Stephen Purcell

    IPC分类号： G09G5/00

    CPC分类号： G06T15/06 ,  G06T15/005 ,  G06T15/50 ,  G06T15/80

    摘要： Ray tracing scenes is accomplished using a plurality of intersection testing resources coupled with a plurality of shading resources, communicative in the aggregate through links/queues. A queue from testing to shading comprises respective ray/primitive intersection indications, comprising a ray identifier. A queue from shading to testing comprises identifiers of new rays to be tested, wherein data defining the rays is separately stored in memories distributed among the intersection testing resources. Ray definition data can be retained in distributed memories until rays complete intersection testing, and be selected for testing multiple times based on ray identifier. A structure of acceleration shapes can be used. Packets of ray identifiers and shape data can be passed among the intersection testing resources, and each resource can test rays identified in the packet, and for which definition data is present in its memory. Test results for acceleration shapes are used to collect rays against acceleration shapes, and closest detection ray/primitive intersections are indicated by sending ray identifiers to shading resources.

    摘要翻译： 光线跟踪场景是利用与多个着色资源相结合的多个交叉点测试资源来实现的，通过链路/队列在聚合中进行通信。 从测试到阴影的队列包括相应的射线/原始相交指示，包括射线标识符。 从阴影到测试的队列包括要测试的新射线的标识符，其中定义射线的数据被分别存储在分布在交叉点测试资源之间的存储器中。 光线定义数据可以保留在分布式存储器中，直到光线完成相交测试，并根据光线标识符多次选择进行测试。 可以使用加速形状的结构。 光线标识符和形状数据的包可以在交叉点测试资源之间传递，并且每个资源可以测试在分组中标识的射线，并且其存储在哪个定义数据中。 加速度形状的测试结果用于收集与加速度形状相对应的射线，最近的检测射线/原始相交是通过将遮蔽资源发送射线标识符来表示的。

    Architectures for parallelized intersection testing and shading for ray-tracing rendering
    10.
    发明授权
    Architectures for parallelized intersection testing and shading for ray-tracing rendering 有权
    用于光线跟踪渲染的并行交叉测试和阴影的架构

    公开(公告)号：US08203559B2

    公开(公告)日：2012-06-19

    申请号：US12941884

    申请日：2010-11-08

    申请人： Luke Tilman Peterson ,  James Alexander McCombe ,  Ryan R. Salsbury ,  Stephen Purcell

    发明人： Luke Tilman Peterson ,  James Alexander McCombe ,  Ryan R. Salsbury ,  Stephen Purcell

    IPC分类号： G06T15/50

    CPC分类号： G06T15/06 ,  G06T15/005 ,  G06T15/50 ,  G06T15/80

    摘要： Ray tracing scenes is accomplished using a plurality of intersection testing resources coupled with a plurality of shading resources, communicative in the aggregate through links/queues. A queue from testing to shading comprises respective ray/primitive intersection indications, comprising a ray identifier. A queue from shading to testing comprises identifiers of new rays to be tested, wherein data defining the rays is separately stored in memories distributed among the intersection testing resources. Ray definition data can be retained in distributed memories until rays complete intersection testing, and be selected for testing multiple times based on ray identifier. A structure of acceleration shapes can be used. Packets of ray identifiers and shape data can be passed among the intersection testing resources, and each resource can test rays identified in the packet, and for which definition data is present in its memory. Test results for acceleration shapes are used to collect rays against acceleration shapes, and closest detection ray/primitive intersections are indicated by sending ray identifiers to shading resources.

    摘要翻译： 光线跟踪场景是利用与多个着色资源相结合的多个交叉点测试资源来实现的，通过链路/队列在聚合中进行通信。 从测试到阴影的队列包括相应的射线/原始相交指示，包括射线标识符。 从阴影到测试的队列包括要测试的新射线的标识符，其中定义射线的数据被分别存储在分布在交叉点测试资源之间的存储器中。 光线定义数据可以保留在分布式存储器中，直到光线完成相交测试，并根据光线标识符多次选择进行测试。 可以使用加速形状的结构。 光线标识符和形状数据的包可以在交叉点测试资源之间传递，并且每个资源可以测试在分组中标识的射线，并且其存储在哪个定义数据中。 加速度形状的测试结果用于收集与加速度形状相对应的射线，最近的检测射线/原始相交是通过将遮蔽资源发送射线标识符来表示的。