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公开(公告)号：US07191379B2
公开(公告)日：2007-03-13
申请号：US10659630
申请日：2003-09-10
CPC分类号： G11C11/15 , G06F11/1008 , G06F2211/109
摘要： Embodiments of the present invention are implemented in memory systems. In one embodiment, the memory comprises an array of memory cells and a control circuit. The control circuit is configured to read error correction coded data from the array of memory cells, provide error correction code decoding to selected error correction coded data and discard unused error correction code parity data of unselected error correction coded data.
摘要翻译： 本发明的实施例在存储器系统中实现。 在一个实施例中，存储器包括存储器单元阵列和控制电路。 控制电路被配置为从存储器单元阵列读取纠错编码数据，向所选择的纠错编码数据提供纠错码解码，并丢弃未选择的纠错编码数据的未使用的纠错码奇偶校验数据。
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公开(公告)号：US07418644B2
公开(公告)日：2008-08-26
申请号：US10790360
申请日：2004-03-01
IPC分类号： H03M13/29
CPC分类号： H03M13/3761 , H03M13/09 , H03M13/1515 , H03M13/19 , H03M13/23 , H03M13/3707
摘要： A system for error correction coding and decoding information is disclosed. In one embodiment, the first and second encoders are each configured to encode the information, wherein the second encoder has a higher capability than the first encoder. First and second decoders are configured to recover the information, wherein the second decoder recovers the information encoded by the second encoder only if the first decoder cannot recover the information.
摘要翻译： 公开了一种用于纠错编码和解码信息的系统。 在一个实施例中，第一和第二编码器各自被配置为对信息进行编码，其中第二编码器具有比第一编码器更高的能力。 第一和第二解码器被配置为恢复信息，其中第二解码器仅在第一解码器不能恢复信息时才恢复由第二编码器编码的信息。
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3.发明授权Assisted memory device for reading and writing single and multiple units of data 有权辅助存储设备用于读写单个和多个单元的数据公开(公告)号：US07149950B2
公开(公告)日：2006-12-12
申请号：US10661937
申请日：2003-09-12
IPC分类号： G11C29/00
CPC分类号： G06F13/16 , G06F11/076 , G06F11/1008
摘要： A device comprises a memory array in which a plurality of codewords is stored. Each codeword comprises an error correction code and a data block that comprises a plurality of units of data. The device further comprises an error code correction module coupled to the memory array. When multiple units of data are to be read from the device for an address, a codeword stored in a location associated with the address is fetched from the memory array, the error code correction module decodes the codeword and corrects any errors in the data block for that codeword, and the multiple units of data are read from the corrected data block.
摘要翻译： 一种设备包括其中存储多个码字的存储器阵列。 每个码字包括纠错码和包括多个数据单元的数据块。 该设备还包括耦合到存储器阵列的错误代码校正模块。 当从设备读取地址的多个单元数据时，存储在与地址相关联的位置的代码字从存储器阵列中取出，错误代码校正模块解码码字并且校正数据块中的任何错误 从校正的数据块中读取该码字和多个数据单元。
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4.发明授权Manufacturing test for a fault tolerant magnetoresistive solid-state storage device 有权一种容错磁阻固态存储装置的制造试验公开(公告)号：US07149948B2
公开(公告)日：2006-12-12
申请号：US09997199
申请日：2001-11-28
申请人： James A. Davis , Jonathan Jedwab , Stephen Morley , Kenneth Graham Paterson , Frederick A. Perner , Kenneth K. Smith , Stewart R. Wyatt
发明人： James A. Davis , Jonathan Jedwab , Stephen Morley , Kenneth Graham Paterson , Frederick A. Perner , Kenneth K. Smith , Stewart R. Wyatt
IPC分类号： G11C29/00
CPC分类号： G11C11/16
摘要： A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical defects. At manufacture, the MRAN device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data, using either a parametric evaluation (step 602), or a logical evaluation (step 603) or preferably a combination of both. Failed cells are identified and a count is formed, suitably in terms of ECC symbols 206 that would be affected by such failed cells (step 604). The count can be compared to a threshold (step 605) to determine suitability of the accessed storage cells and a decision made (step 606) on whether to continue with use of those cells, or whether to take remedial action.
摘要翻译： 使用的容错磁阻固态存储装置（MRAM）对所存储的信息进行纠错编码和解码，以容忍物理缺陷。 在制造时，使用参数评估（步骤602）或逻辑评估（步骤603）或优选两者的组合来测试MRAN设备以确认每组存储单元适合于存储ECC编码数据。 识别失败的单元并且适当地根据将被这种故障单元影响的ECC符号206形成计数（步骤604）。 可以将计数与阈值进行比较（步骤605）以确定所访问的存储单元的适合性以及对是否继续使用这些单元或者是否采取补救动作的决定（步骤606）。
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5.发明授权Systems and methods for controlling communication with nonvolatile memory devices 有权用于控制与非易失性存储器件通信的系统和方法公开(公告)号：US06976143B2
公开(公告)日：2005-12-13
申请号：US10008101
申请日：2001-11-13
CPC分类号： G06F12/0661
摘要： Systems and methods for controlling communication with nonvolatile memory devices via a memory bus are provided. Briefly described, one of many possible embodiments is a system comprising a memory controller in communication with a memory bus, the memory controller configured to control communication with at least one nonvolatile memory device by configuring the at least one nonvolatile memory device, via the memory bus, with a unique device identifier.
摘要翻译： 提供了通过存储器总线来控制与非易失性存储器件的通信的系统和方法。 简要描述，许多可能的实施例之一是包括与存储器总线通信的存储器控制器的系统，所述存储器控制器被配置为通过经由存储器总线配置所述至少一个非易失性存储器设备来控制与至少一个非易失性存储器设备的通信 ，具有唯一的设备标识符。
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6.发明授权Buffer management for data transfers between a host device and a storage medium 有权用于在主机设备和存储介质之间进行数据传输的缓冲区管理公开(公告)号：US07421459B2
公开(公告)日：2008-09-02
申请号：US10091778
申请日：2002-03-06
IPC分类号： G06F17/30
CPC分类号： G06F5/14 , G06F2205/108 , Y10S707/99955
摘要： Systems and methods for transferring data between a host device and a storage medium are provided. In one implementation, a system for transferring data between a host device and a storage medium includes a host interface that receives from the host device a command to transfer data between the host device and the storage medium, a buffer that temporarily stores data that is transferred between the host device and the storage medium, a first register that stores a value for tracking a number of data units that have been transferred into the buffer but that have not yet been transferred out of the buffer, a second register that stores a value for incrementing a value contained in the first register, and a third register that stores a value for decrementing a value contained in the first register.
摘要翻译： 提供了用于在主机设备和存储介质之间传送数据的系统和方法。 在一个实现中，用于在主机设备和存储介质之间传送数据的系统包括主机接口，主机接口从主机设备接收在主设备和存储介质之间传送数据的命令，临时存储传输的数据的缓冲器 在所述主机设备和所述存储介质之间存储第一寄存器，所述第一寄存器存储用于跟踪已经被传送到所述缓冲器中但尚未被传送到所述缓冲器的数据单元的数量的值;第二寄存器， 增加包含在第一寄存器中的值，以及第三寄存器，其存储用于递减包含在第一寄存器中的值的值。
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公开(公告)号：US06968479B2
公开(公告)日：2005-11-22
申请号：US10092111
申请日：2002-03-06
CPC分类号： G06F11/10
摘要： The present invention relates to a storage device controller for controlling the operations of the data storage system. The controller includes error-correcting code (ECC) coding and decoding of data stored on media of the data storage system. A Verify procedure of the present invention is performed which verifies the validity of the data written to the media. The Verify procedure runs continuously until an error is detected or until an external event terminates the procedure. By accessing a range of memory addresses in the media and by resetting an address counter to a start of the range of addresses after a last address of the range has been accessed, the Verify procedure continuously checks the memory locations for errors. The range of addresses may include all of the accessible addresses in the data storage device. Additionally, information on the quality of the media may be collected and used to determine how much the media deteriorates over time. Sparing of defective memory locations may also be provided, even after manufacturing and packaging of the data storage system.
摘要翻译： 本发明涉及一种用于控制数据存储系统的操作的存储设备控制器。 该控制器包括对存储在数据存储系统的媒体上的数据的纠错码（ECC）编码和解码。 执行本发明的验证过程，其验证写入介质的数据的有效性。 验证过程持续运行，直到检测到错误或直到外部事件终止该过程。 通过访问媒体中的一系列存储器地址，并且在访问了该范围的最后一个地址之后，通过将地址计数器重新设置为地址范围的开始，验证过程会连续检查存储器位置是否存在错误。 地址范围可以包括数据存储设备中的所有可访问地址。 此外，可以收集关于媒体质量的信息并用于确定媒体随时间恶化的程度。 即使在数据存储系统的制造和封装之后，也可以提供缺陷存储器位置。
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公开(公告)号：US06629168B1
公开(公告)日：2003-09-30
申请号：US09595581
申请日：2000-06-15
申请人： Kimberly K. Kroll , Paula D. Repman , Charles D. Smith , R. Alexis Takasugi , Stewart R. Wyatt , Mark J. Simms , Julie Hogan , Thomas Carter , Fintan Buckley
发明人： Kimberly K. Kroll , Paula D. Repman , Charles D. Smith , R. Alexis Takasugi , Stewart R. Wyatt , Mark J. Simms , Julie Hogan , Thomas Carter , Fintan Buckley
IPC分类号： G06F300
摘要： Byte-swapping in a buffer memory system utilizes a byte-swapping register to avoid wasteful unused buffer memory spaces that may result from a data transfer of partial word data, i.e., bytes of data less than the number of bytes in a word, to the buffer memory. When a data transfer request, e.g., a write request, requires a transfer of a partial word, the partial request is written to a word in the buffer memory, and is also stored in the byte-swapping register. In a subsequent data transfer request, the partial word stored in the byte-swapping register is combined and concatenated with sufficient bytes of data of the subsequent data transfer request to produce a complete word. The complete word is written in the word in the buffer memory, replacing the previously stored partial word, and thus fills the previously unused buffer memory space.
摘要翻译： 缓冲存储器系统中的字节交换利用字节交换寄存器来避免浪费的未使用的缓冲存储空间，这些空间可能是由于部分字数据的数据传输，即数据字节数字小于单词中的字节数， 缓冲存储器 当数据传输请求（例如写入请求）需要传送部分字时，部分请求被写入缓冲存储器中的字，并且还存储在字节交换寄存器中。 在随后的数据传输请求中，存储在字节交换寄存器中的部分字被组合并与后续数据传送请求的足够数据字节连接以产生完整字。 将完整的单词写入缓冲存储器中的单词，替换先前存储的部分单词，从而填充以前未使用的缓冲区内存空间。
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9.发明授权System having a storage controller that modifies operation of a storage system based on the status of a data transfer 有权具有存储控制器的系统，其基于数据传送的状态来修改存储系统的操作公开(公告)号：US07213086B2
公开(公告)日：2007-05-01
申请号：US10695363
申请日：2003-10-28
申请人： Stewart R. Wyatt , Andrew M. Spencer , Robert G. Mejia , Connie K. Lemus , Kenneth J. Eldredge , Cyrille de Brebisson
发明人： Stewart R. Wyatt , Andrew M. Spencer , Robert G. Mejia , Connie K. Lemus , Kenneth J. Eldredge , Cyrille de Brebisson
CPC分类号： G06F3/0656 , G06F1/3203 , G06F1/325 , G06F1/3256 , G06F1/3268 , G06F1/3275 , G06F3/0625 , G06F3/0674 , G06F13/16 , Y02D10/14 , Y02D10/154 , Y02D10/1542
摘要： A system comprises a storage controller for managing transfers of data between a host and storage memory; a data mover coupled to the storage controller handling data transferred between a host and storage memory; and a buffer coupled to the data mover for storing data being transferred. The storage controller modifies operation of the storage system based on status of the data transfer. An associate method comprises transferring data between a host and storage memory via a storage system, and dynamically adjusting operation of the storage system depending on status of the data transfer.
摘要翻译： 一种系统，包括：存储控制器，用于管理主机与存储存储器之间的数据传输; 耦合到存储控制器的数据移动器，处理在主机和存储存储器之间传送的数据; 以及耦合到所述数据移动器的用于存储要传送的数据的缓冲器。 存储控制器基于数据传输的状态来修改存储系统的操作。 关联方法包括经由存储系统在主机和存储存储器之间传送数据，以及根据数据传输的状态动态调整存储系统的操作。
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公开(公告)号：US06865108B2
公开(公告)日：2005-03-08
申请号：US10614581
申请日：2003-07-07
CPC分类号： G11C11/15
摘要： A data storage device that includes a memory cell string. The memory cell string includes a first memory cell and a second memory cell. The device also includes a circuit coupled to a node between the first memory cell and a second memory cell. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and the first memory cell being written to a first state.
摘要翻译： 一种包括存储单元串的数据存储装置。 存储单元串包括第一存储单元和第二存储单元。 该装置还包括耦合到第一存储单元和第二存储单元之间的节点的电路。 电路被配置为响应于提供给存储器单元串并且第一存储器单元被写入第一状态的电压来检测节点处的电压变化。
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