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公开(公告)号:US09786523B2
公开(公告)日:2017-10-10
申请号:US14211303
申请日:2014-03-14
Applicant: TOKYO ELECTRON LIMITED
Inventor: Carlos A Fonseca , Michael A Carcasi
CPC classification number: H01L21/67051 , B08B3/00 , B08B3/02 , B08B3/024 , B08B3/04 , B08B3/041 , B08B5/00 , B08B5/02 , H01L21/02052 , H01L21/67028 , H01L21/67034 , H01L21/6704
Abstract: A method and apparatus are disclosed for optimizing a rinsing and drying process in semiconductor manufacturing. The optimization seeks to maximize processing throughput while maintaining low defect counts and high device yields, and utilizes simulation and experimental data to set the optimal process parameters for the rinsing and drying process. Improved methods of rinse liquid and purge gas nozzle movement are also disclosed.
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公开(公告)号:US09281251B2
公开(公告)日:2016-03-08
申请号:US14453352
申请日:2014-08-06
Applicant: Tokyo Electron Limited
Inventor: Carlos A Fonseca , Anton Devilliers , Benjamen M Rathsack , Jeffrey T Smith , Lior Huli
IPC: C23F1/00 , H01L21/66 , H01L21/306 , G03F7/20
CPC classification number: H01L21/02016 , G03F7/70783 , H01L21/30625 , H01L21/687 , H01L22/12 , H01L22/20
Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.
Abstract translation: 所描述的实施例涉及一种减小光刻畸变的方法和装置。 半导体衬底的背面可以被组织化。 然后可以在具有纹理化背面的半导体衬底上进行光刻工艺。
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