公开(公告)号：US09281251B2

公开(公告)日：2016-03-08

申请号：US14453352

申请日：2014-08-06

Applicant: Tokyo Electron Limited

Inventor： Carlos A Fonseca ,  Anton Devilliers ,  Benjamen M Rathsack ,  Jeffrey T Smith ,  Lior Huli

IPC: C23F1/00 ,  H01L21/66 ,  H01L21/306 ,  G03F7/20

CPC classification number: H01L21/02016 ,  G03F7/70783 ,  H01L21/30625 ,  H01L21/687 ,  H01L22/12 ,  H01L22/20

Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

Abstract translation: 所描述的实施例涉及一种减小光刻畸变的方法和装置。 半导体衬底的背面可以被组织化。 然后可以在具有纹理化背面的半导体衬底上进行光刻工艺。

公开(公告)号：US11764113B2

公开(公告)日：2023-09-19

申请号：US17392997

申请日：2021-08-03

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Daniel Chanemougame ,  Lars Liebmann ,  Paul Gutwin ,  Robert Clark ,  Anton Devilliers

IPC: H01L21/8238 ,  H01L23/00 ,  H01L21/324 ,  H01L21/306

CPC classification number: H01L21/823807 ,  H01L21/306 ,  H01L21/324 ,  H01L24/83 ,  H01L2224/83896

Abstract: Techniques herein include methods for fabricating CFET devices. The methods enable high-temperature processes to be performed for FINFET and gate all around (GAA) technologies without degradation of temperature sensitive materials within the device and transistors. In particular, high temperature anneals and depositions can be performed prior to deposition of temperature-sensitive materials, such as work function metals and silicides. The methods enable at least two transistor devices to be fabricated in a stepwise manner while preventing thermal violations of any materials in either transistor.

公开(公告)号：US10991626B2

公开(公告)日：2021-04-27

申请号：US16898014

申请日：2020-06-10

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Subhadeep Kal ,  Anton Devilliers

IPC: H01L21/822 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/308 ,  H01L21/306 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/10 ,  H01L29/786 ,  H01L27/06

Abstract: A semiconductor device includes: a substrate having a planar surface; a first gate-all-around field effect transistor (GAA-FET) provided on said substrate and comprising a first channel having an untrimmed volume of first channel material corresponding to a volume of the first channel material within a first stacked fin structure from which the first channel was formed; and a second GAA-FET provided on said substrate and comprising a second channel having a trimmed volume of second channel material which is less than said untrimmed volume of first channel material by a predetermined trim amount corresponding to a delay adjustment of the second GAA-FET relative to the first GAA-FET, wherein said first and second GAA FETs are electrically connected as complementary FETs.

公开(公告)号：US20190057867A1

公开(公告)日：2019-02-21

申请号：US15998509

申请日：2018-08-16

Applicant: TOKYO ELECTRON LIMITED

Inventor： Jeffrey Smith ,  Anton Devilliers

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

Abstract: A method of forming a semiconductor device includes providing a starting structure including a substrate having thereon a plurality of gate regions alternately arranged with a plurality of source/drain (S/D) regions, wherein each of the gate regions includes a nanochannel structure having an intermediate portion surrounded by a replacement gate, and opposing end portions surrounded by respective gate spacers such that the nanochannel structure extends through the replacement gate and the gate spacers of the gate region. Each of the S/D regions includes an S/D structure extending through the S/D region to connect nanochannel structures of first and second adjacent gate regions provided on opposing sides of the S/D region respectively. The first adjacent gate region is converted into a single diffusion break including a dummy gate structure, and the second adjacent gate region is converted into an active gate including an active gate structure configured to create a current channel within the nanochannel structure of the second adjacent gate region.

公开(公告)号：US12099299B2

公开(公告)日：2024-09-24

申请号：US18354388

申请日：2023-07-18

Applicant: Tokyo Electron Limited

Inventor： Jodi Grzeskowiak ,  Anthony Schepis ,  Anton Devilliers

IPC: G03F7/09 ,  G03F7/004 ,  G03F7/11 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308

CPC classification number: G03F7/094 ,  G03F7/0045 ,  G03F7/091 ,  G03F7/11 ,  H01L21/0276 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

公开(公告)号：US11721582B2

公开(公告)日：2023-08-08

申请号：US17557561

申请日：2021-12-21

Applicant: Tokyo Electron Limited

Inventor： Mark I. Gardner ,  H. Jim Fulford ,  Anton Devilliers

IPC: H01L21/768 ,  H01L21/306 ,  H01L23/48 ,  H01L21/822 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L21/30608 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/53257

Abstract: Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silicon stacks. A first portion can be masked while a second, uncovered portion is etched. Predetermined layers in a bottom portion (disposed closer to the substrate) of the multilayer stack can be replaced with a conductor. The second portion can be masked while the first portion is uncovered and processed. This can enable higher density 3D circuits by having multiple metal lines contained within a multilayer 3D nano-sheet. Advantageously, this facilitates easier connections for 3D logic and memory. Moreover, better speed performance can be achieved by having reduced distance for signals to travel to transistor connections.

公开(公告)号：US11322401B2

公开(公告)日：2022-05-03

申请号：US17034930

申请日：2020-09-28

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Lars Liebmann ,  Daniel Chanemougame ,  Hiroki Niimi ,  Kandabara Tapily ,  Subhadeep Kal ,  Jodi Grzeskowiak ,  Anton Devilliers

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.

公开(公告)号：US11782346B2

公开(公告)日：2023-10-10

申请号：US17032980

申请日：2020-09-25

Applicant: Tokyo Electron Limited

Inventor： Jodi Grzeskowiak ,  Anthony Schepis ,  Anton Devilliers

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  G03F7/004 ,  G03F7/11

CPC classification number: G03F7/094 ,  G03F7/0045 ,  G03F7/091 ,  G03F7/11 ,  H01L21/0276 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

公开(公告)号：US11251080B2

公开(公告)日：2022-02-15

申请号：US16848213

申请日：2020-04-14

Applicant: Tokyo Electron Limited

Inventor： Mark I. Gardner ,  H. Jim Fulford ,  Anton Devilliers

IPC: H01L21/768 ,  H01L21/306 ,  H01L23/48 ,  H01L21/822 ,  H01L23/532

Abstract: Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silicon stacks. A first portion can be masked while a second, uncovered portion is etched. Predetermined layers in a bottom portion (disposed closer to the substrate) of the multilayer stack can be replaced with a conductor. The second portion can be masked while the first portion is uncovered and processed. This can enable higher density 3D circuits by having multiple metal lines contained within a multilayer 3D nano-sheet. Advantageously, this facilitates easier connections for 3D logic and memory. Moreover, better speed performance can be achieved by having reduced distance for signals to travel to transistor connections.

公开(公告)号：US10714391B2

公开(公告)日：2020-07-14

申请号：US16204605

申请日：2018-11-29

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Subhadeep Kal ,  Anton Devilliers

IPC: H01L27/12 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/308 ,  H01L21/306 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/10 ,  H01L29/786 ,  H01L27/06

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate including a first stacked fin structure for forming a channel of a first gate-all-around (GAA) transistor, the first stacked fin structure including an initial volume of first channel material, and a second stacked fin structure for forming a channel of a second GAA transistor, the second stacked fin structure including an initial volume of second channel material; reducing said initial volume of the second channel material relative to the initial volume of first channel material by a predetermined amount corresponding to a delay of the first GAA transistor; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.