公开(公告)号：US20060220110A1

公开(公告)日：2006-10-05

申请号：US11421047

申请日：2006-05-30

申请人： Tommy Lai ,  Pradeep Yelehanka ,  Jia Zhen Zheng ,  Weining Li

发明人： Tommy Lai ,  Pradeep Yelehanka ,  Jia Zhen Zheng ,  Weining Li

IPC分类号： H01L29/792 ,  H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L21/022 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31155 ,  H01L21/3144 ,  H01L27/1052 ,  H01L27/11546

摘要： An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

摘要翻译： 集成电路结构包括提供半导体衬底并在半导体衬底上形成至少一个氧化物 - 氮化物 - 氧化物电介质层。 在形成氧化物 - 氮化物 - 氧化物电介质层之后，至少一个注入形成在氧化物 - 氮化物 - 氧化物介电层下方的半导体衬底的至少一个区域中。

公开(公告)号：US20060214185A1

公开(公告)日：2006-09-28

申请号：US11422560

申请日：2006-06-06

申请人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Yelehanka

发明人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Yelehanka

IPC分类号： H01L29/74

CPC分类号： H01L27/11 ,  H01L27/0617 ,  H01L29/66393 ,  H01L29/7436

摘要： An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

摘要翻译： 集成电路结构包括提供半导体衬底并在其中形成沟槽。 在沟槽周围和半导体衬底内形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 晶闸管的栅极形成在沟槽内。 在半导体衬底上形成存取晶体管。 在晶闸管和存取晶体管之间形成互连。

公开(公告)号：US20050167664A1

公开(公告)日：2005-08-04

申请号：US11077731

申请日：2005-03-10

申请人： Elgin Quek ,  Jia Zheng ,  Pradeep Yelehanka ,  Weining Li

发明人： Elgin Quek ,  Jia Zheng ,  Pradeep Yelehanka ,  Weining Li

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/66378 ,  H01L29/66393 ,  H01L29/66795

摘要： An integrated circuit structure includes a semiconductor substrate and a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor is in contact with the thyristor.

摘要翻译： 集成电路结构包括在半导体衬底的顶部上的半导体衬底和水平半导体鳍片。 存取晶体管栅极和晶闸管栅极位于半导体衬底的顶部并且与水平半导体鳍片接触。 存取晶体管是水平半导体鳍片和存取晶体管栅极的至少一部分。 晶闸管是水平半导体鳍片和晶闸管栅极的至少一部分，存取晶体管与晶闸管接触。

公开(公告)号：US20050026343A1

公开(公告)日：2005-02-03

申请号：US10629041

申请日：2003-07-28

申请人： Elgin Quek ,  Jia Zheng ,  Pradeep Yelehanka ,  Weining Li

发明人： Elgin Quek ,  Jia Zheng ,  Pradeep Yelehanka ,  Weining Li

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/332

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/66378 ,  H01L29/66393 ,  H01L29/66795

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are then formed on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is formed from at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is formed from at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor being in contact with the thyristor.

摘要翻译： 一种用于制造集成电路结构的方法包括：在半导体衬底的顶部上提供半导体衬底和形成水平半导体鳍片。 然后在半导体衬底的顶部上形成存取晶体管栅极和晶闸管栅极，并与水平半导体鳍片接触。 存取晶体管由水平半导体鳍片和存取晶体管栅极的至少一部分形成。 晶闸管由水平半导体鳍片和晶闸管栅极的至少一部分形成，存取晶体管与晶闸管接触。

公开(公告)号：US20090156010A1

公开(公告)日：2009-06-18

申请号：US11959034

申请日：2007-12-18

申请人： Xiang Hu ,  Hai Cong ,  Pradeep Yelehanka ,  Mei Sheng Zhou

发明人： Xiang Hu ,  Hai Cong ,  Pradeep Yelehanka ,  Mei Sheng Zhou

IPC分类号： H01L21/302

CPC分类号： H01J37/32963 ,  H01J37/32935

摘要： A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.

摘要翻译： 一种用于蚀刻薄膜并制造半导体器件的方法包括：在监测从基板远离的端点检测层的移除的同时，对衬底上的薄膜进行蚀刻，从而通过监测薄膜蚀刻来精确控制薄膜蚀刻 移除端点检测层。 端点检测层形成在暴露于与要蚀刻的薄膜相同的蚀刻条件的蚀刻装置的表面上。 当从蚀刻装置的表面去除预定量的端点检测层时，停止对薄膜的蚀刻。

公开(公告)号：US06884712B2

公开(公告)日：2005-04-26

申请号：US10359975

申请日：2003-02-07

申请人： Pradeep Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Zhen Jia Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

发明人： Pradeep Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Zhen Jia Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6656

摘要： An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

摘要翻译： 提供了一种集成电路及其制造方法。 分别在半导体衬底上和上方提供栅极电介质和栅极。 在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。 间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。 第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。 在第一电介质层上形成第二电介质层。 局部互连开口形成在第二电介质层中，直到第一电介质层。 打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。 第一和第二介电层中的局部互连开口用导电材料填充。

公开(公告)号：US08940616B2

公开(公告)日：2015-01-27

申请号：US13559626

申请日：2012-07-27

申请人： Rama Krishna Kotlanka ,  Rakesh Kumar ,  Premachandran Chirayarikathuveedu Sankarapillai ,  Huamao Lin ,  Pradeep Yelehanka

发明人： Rama Krishna Kotlanka ,  Rakesh Kumar ,  Premachandran Chirayarikathuveedu Sankarapillai ,  Huamao Lin ,  Pradeep Yelehanka

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/76 ,  H01L21/00

CPC分类号： B81B7/0006 ,  B81C1/00269 ,  B81C3/001 ,  B81C2201/0115 ,  H01L21/50 ,  H01L23/481 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

摘要翻译： 公开了具有至少一个孔隙化表面的粘合装置。 孔化过程将纳米多孔孔引入装置的结合表面的微结构中。 与非孔隙化材料相比，孔化材料的材料性质更软。 对于相同的接合条件，与非孔隙化材料相比，使用孔隙化粘合表面增强了粘结界面的粘结强度。

公开(公告)号：US07323736B2

公开(公告)日：2008-01-29

申请号：US11438188

申请日：2006-05-22

申请人： Pradeep Yelehanka ,  Sanford Chu ,  Chit Hwei Ng ,  Jia Zhen ,  Purakh Verma

发明人： Pradeep Yelehanka ,  Sanford Chu ,  Chit Hwei Ng ,  Jia Zhen ,  Purakh Verma

IPC分类号： H01L27/108

CPC分类号： H01L28/55 ,  H01L21/02109 ,  H01L21/3127 ,  H01L21/3144 ,  H01L21/31625 ,  H01L21/31629 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10T428/12035 ,  H01L2924/00

摘要： A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.

摘要翻译： 一种提供用于在具有高和低介电常数的半导体材料的一个平面层中形成的新方法。 具有选择且优选不相同的介电常数参数的层被依次沉积，散布有蚀刻停止材料层。 这些层可以被蚀刻，在那里形成开口，通过这些层可以填充一层选择。

公开(公告)号：US07879732B2

公开(公告)日：2011-02-01

申请号：US11959034

申请日：2007-12-18

申请人： Xiang Hu ,  Hai Cong ,  Pradeep Yelehanka ,  Mei Sheng Zhou

发明人： Xiang Hu ,  Hai Cong ,  Pradeep Yelehanka ,  Mei Sheng Zhou

IPC分类号： H01L21/302 ,  G01R31/00 ,  B44C1/22

CPC分类号： H01J37/32963 ,  H01J37/32935

摘要： A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.

摘要翻译： 一种用于蚀刻薄膜并制造半导体器件的方法包括：在监测从基板远离的端点检测层的移除的同时，对衬底上的薄膜进行蚀刻，从而通过监测薄膜蚀刻来精确控制薄膜蚀刻 移除端点检测层。 端点检测层形成在暴露于与要蚀刻的薄膜相同的蚀刻条件的蚀刻装置的表面上。 当从蚀刻装置的表面去除预定量的端点检测层时，停止对薄膜的蚀刻。

公开(公告)号：US07060193B2

公开(公告)日：2006-06-13

申请号：US10189876

申请日：2002-07-05

申请人： Pradeep Yelehanka ,  Sanford Chu ,  Chit Hwei Ng ,  Jia Zhen ,  Purakh Verma

发明人： Pradeep Yelehanka ,  Sanford Chu ,  Chit Hwei Ng ,  Jia Zhen ,  Purakh Verma

IPC分类号： H01B13/00

CPC分类号： H01L28/55 ,  H01L21/02109 ,  H01L21/3127 ,  H01L21/3144 ,  H01L21/31625 ,  H01L21/31629 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10T428/12035 ,  H01L2924/00

摘要： A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.

摘要翻译： 一种提供用于在具有高和低介电常数的半导体材料的一个平面层中形成的新方法。 具有选择且优选不相同的介电常数参数的层被依次沉积，散布有蚀刻停止材料层。 这些层可以被蚀刻，在那里形成开口，通过这些层可以填充一层选择。