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9 条记录 (耗时 0.031 秒)

    Charge pump circuit
    4.
    发明授权
    Charge pump circuit 有权
    电荷泵电路

    公开(公告)号：US07342437B2

    公开(公告)日：2008-03-11

    申请号：US11337467

    申请日：2006-01-24

    申请人： Yoshitaka Onaya ,  Tatsuya Suzuki

    发明人： Yoshitaka Onaya ,  Tatsuya Suzuki

    IPC分类号： G05F1/10

    CPC分类号： H02M3/07

    摘要： A size of a charge pump circuit is reduced as well as its cost. In a positive booster charge pump circuit in an embodiment of this invention, a positive boosted voltage 2VDD generated at its first stage node is used as a gate voltage to turn on a MOS transistor that outputs a high level (VDD) of each of the first, third and fourth clock drivers. And in a negative charge pump circuit, a negative boosted voltage −VDD generated at its first stage node is used as a gate voltage to turn on a MOS transistor that outputs a high level of each of the second and fifth clock drivers.

    摘要翻译： 电荷泵电路的尺寸以及其成本降低。 在本发明的一个实施例中的正升压电荷泵电路中，在其第一级节点处产生的正升压电压2VDD用作栅极电压，以导通输出高电平（VDD）的MOS晶体管， ，第三和第四个时钟驱动程序。 在负电荷泵电路中，在其第一级节点处产生的负升压电压-VDD用作栅极电压，以导通输出第二和第五时钟​​驱动器中的每一个的高电平的MOS晶体管。

    Echo prevention circuit, filter coefficient setting method, and recording medium with program recorded
    5.
    发明授权
    Echo prevention circuit, filter coefficient setting method, and recording medium with program recorded 有权
    回波防止电路，滤波器系数设定方法和记录有程序的记录介质

    公开(公告)号：US07400278B2

    公开(公告)日：2008-07-15

    申请号：US11681643

    申请日：2007-03-02

    申请人： Takeo Inoue ,  Hideki Ohashi ,  Yoshitaka Onaya

    发明人： Takeo Inoue ,  Hideki Ohashi ,  Yoshitaka Onaya

    IPC分类号： H03M1/00

    CPC分类号： H04M9/082

    摘要： An echo prevention circuit includes a filter that receives a first digital signal and outputs second and third digital signals; first and second DA converter that convert the second and third digital signals into first and second analog signals respectively; a circuit to subtract the second analog signal from a signal generated by combining the first analog signal and a third analog signal, a circuit to amplify the signal from the subtracting circuit; an AD converter that converts the amplified signal into a digital signal; a responsive signal acquiring unit to acquire a first response signal from the input of the first DA converter to the output of the AD converter and to acquire a second response signal from the input of the second DA converter to the output of the AD converter; and a unit to set filter coefficients based on the first and second response signals.

    摘要翻译： 回波防止电路包括：接收第一数字信号并输出​​第二和第三数字信号的滤波器; 第一和第二DA转换器，分别将第二和第三数字信号转换成第一和第二模拟信号; 从通过组合第一模拟信号和第三模拟信号而产生的信号中减去第二模拟信号的电路，放大来自减法电路的信号的电路; AD转换器，将放大的信号转换成数字信号; 响应信号获取单元，用于从第一DA转换器的输入到AD转换器的输出获取第一响应信号，并从第二DA转换器的输入到AD转换器的输出获取第二响应信号; 以及基于第一和第二响应信号来设置滤波器系数的单元。

    Charge pump circuit
    6.
    发明授权
    Charge pump circuit 失效
    电荷泵电路

    公开(公告)号：US07116156B2

    公开(公告)日：2006-10-03

    申请号：US10823004

    申请日：2004-04-13

    申请人： Takao Myono ,  Yoshitaka Onaya

    发明人： Takao Myono ,  Yoshitaka Onaya

    IPC分类号： G05F1/10 ,  G05F3/02

    CPC分类号： H02M3/073 ,  H02M2003/075 ,  H02M2003/076

    摘要： An inrush current at beginning of operation of a charge pump circuit is reduced to prevent adverse effect on other circuits in a system. Charge transfer MOS transistors are connected in series. One end of each coupling capacitor is connected to each connecting point of the charge transfer MOS transistors. An output from each clock driver is applied on the other end of the respective coupling capacitor. Each clock driver includes a first clock driver and a second clock driver having higher driving capacity than the first clock driver. Each clock driver is controlled so that the first clock driver is put into operation at first and at the end of a predetermined elapsed time it is stopped and the second clock driver is put into operation.

    摘要翻译： 降低电荷泵电路运行开始时的浪涌电流，以防止对系统中其他电路的不利影响。 电荷转移MOS晶体管串联连接。 每个耦合电容器的一端连接到电荷转移MOS晶体管的每个连接点。 每个时钟驱动器的输出端施加在相应耦合电容器的另一端。 每个时钟驱动器包括具有比第一时钟驱动器更高的驱动能力的第一时钟驱动器和第二时钟驱动器。 每个时钟驱动器被控制，使得第一时钟驱动器在第一时间和在预定的经过时间结束时被停止并且第二时钟驱动器被投入运行。

    Echo Prevention Circuit, Filter Coefficient Setting Method, and Recording Medium with Program Recorded
    7.
    发明申请
    Echo Prevention Circuit, Filter Coefficient Setting Method, and Recording Medium with Program Recorded 有权

    公开(公告)号：US20070205932A1

    公开(公告)日：2007-09-06

    申请号：US11681643

    申请日：2007-03-02

    申请人： Takeo Inoue ,  Hideki Ohashi ,  Yoshitaka Onaya

    发明人： Takeo Inoue ,  Hideki Ohashi ,  Yoshitaka Onaya

    IPC分类号： H03M1/66

    CPC分类号： H04M9/082

    摘要： An echo prevention circuit comprises a filter that is inputted with a first digital signal, the filter outputting second and third digital signals; a first DA converter that converts the second digital signal into a first analog signal and outputs the first analog signal; a second DA converter that converts the third digital signal into a second analog signal and outputs the second analog signal; an input/output terminal that outputs the first analog signal or that is inputted with a third analog signal; a subtracting circuit that outputs a fourth analog signal acquired by subtracting the second analog signal from a signal generated by combining the first analog signal and the third analog signal; an amplification circuit that amplifies the signal output from the subtracting circuit and outputs the amplified signal; an AD converter that converts the signal output from the amplification circuit into a digital signal and outputs the digital signal; a response signal acquiring unit that inputs a first signal to the first DA converter to acquire a first response signal from the input of the first DA converter to the output of the AD converter, the response signal acquiring unit inputting a second signal to the second DA converter to acquire a second response signal from the input of the second DA converter to the output of the AD converter; and a filter coefficient setting unit that sets filter coefficients to the filter based on the first and second response signals such that the fourth analog signal becomes a signal generated by removing or attenuating the first analog signal from the signal generated by combining the first analog signal and the third analog signal, the amplification circuit setting a gain to a first gain in response to a first control signal input before acquiring the first and second response signals, the amplification circuit setting the gain to a second gain larger than the first gain in response to a second control signal input after acquiring the first and second response signals.

    Charge pump circuit
    8.
    发明申请
    Charge pump circuit 有权
    电荷泵电路

    公开(公告)号：US20060164156A1

    公开(公告)日：2006-07-27

    申请号：US11337467

    申请日：2006-01-24

    申请人： Yoshitaka Onaya ,  Tatsuya Suzuki

    发明人： Yoshitaka Onaya ,  Tatsuya Suzuki

    IPC分类号： G05F1/10

    CPC分类号： H02M3/07

    摘要： A size of a charge pump circuit is reduced as well as its cost. In a positive booster charge pump circuit in an embodiment of this invention, a positive boosted voltage 2 VDD generated at its first stage node is used as a gate voltage to turn on a MOS transistor that outputs a high level (VDD) of each of the first, third and fourth clock drivers. And in a negative charge pump circuit, a negative boosted voltage −VDD generated at its first stage node is used as a gate voltage to turn on a MOS transistor that outputs a high level of each of the second and fifth clock drivers.

    摘要翻译： 电荷泵电路的尺寸以及其成本降低。 在本发明的一个实施例中的正升压器电荷泵电路中，使用在其第一级节点处产生的正升压电压2 VDD作为栅极电压来导通输出高电平（VDD）的MOS晶体管 第一，第三和第四个时钟驱动程序。 在负电荷泵电路中，在其第一级节点处产生的负升压电压-VDD用作栅极电压，以导通输出第二和第五时钟​​驱动器中的每一个的高电平的MOS晶体管。

    Driver circuit
    9.
    发明申请
    Driver circuit 审中-公开
    驱动电路

    公开(公告)号：US20060164135A1

    公开(公告)日：2006-07-27

    申请号：US11337809

    申请日：2006-01-24

    申请人： Takao Myono ,  Yoshitaka Onaya

    发明人： Takao Myono ,  Yoshitaka Onaya

    IPC分类号： H03B1/00

    CPC分类号： H02M1/08 ,  H01L27/0222 ,  H03K17/163

    摘要： An abnormal reduction in a positive high power supply electric potential VH outputted by a positive booster charge pump circuit at switching of an output stage inverter in a driver circuit is prevented. An output of an inverter INV2 is applied to an input terminal of an inverter INV4 for controlling an output transistor, and an output of the inverter INV4 is applied to a gate of an N-channel type MOS transistor of the output stage inverter INV6. The inverter INV4 is made of a P-channel type MOS transistor, a first resistor and an N-channel type MOS transistor connected between a positive high power supply electric potential VH and a negative high power supply electric potential VL, making a connecting node between the first resistor and the N-channel type MOS transistor an output terminal of the inverter INV4.

    摘要翻译： 防止在驱动器电路中的输出级反相器的切换时由正升压器电荷泵电路输出的正高电源电位VH的异常减小。 反相器INV2的输出被施加到用于控制输出晶体管的反相器INV 4的输入端，并且反相器INV4的输出被施加到输出级反相器的N沟道型MOS晶体管的栅极 INV反相器INV4由连接在正高电源电位VH和负高电源电位VL之间的P沟道型MOS晶体管，第一电阻器和N沟道型MOS晶体管构成，使得 在第一电阻器和N沟道型MOS晶体管之间的连接节点是反相器INV4的输出端子。