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    Electrode for p-type Group III nitride compound semiconductor layer and method for producing the same
    3.
    发明授权
    Electrode for p-type Group III nitride compound semiconductor layer and method for producing the same 有权
    p型III族氮化物半导体层用电极及其制造方法

    公开(公告)号：US07190076B2

    公开(公告)日：2007-03-13

    申请号：US10695453

    申请日：2003-10-29

    申请人： Ippei Fujimoto ,  Tsutomu Sekine ,  Miki Moriyama ,  Masanori Murakami ,  Naoki Shibata

    发明人： Ippei Fujimoto ,  Tsutomu Sekine ,  Miki Moriyama ,  Masanori Murakami ,  Naoki Shibata

    IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L29/20 ,  H01L33/00 ,  H01L29/02

    CPC分类号： H01L29/452 ,  H01L21/28575 ,  H01L29/2003 ,  H01L33/32 ,  H01L33/40

    摘要： A GaN layer is formed on a sapphire substrate through an AlN buffer layer and doped with Mg to prepare a laminate (referred to as “GaN substrate”). A metal (Pt and Ni) electrode 50 nm thick is formed on the GaN substrate by (1) vapor deposition after the GaN substrate is heated to a temperature of 300° C. or by (2) vapor deposition while the GaN substrate is left at room temperature. (3) The electrode obtained in (2) is heated to 300° C. in a nitrogen atmosphere. The contact resistance of the electrode obtained in (1) is lower by two or three digits than that of the electrode obtained in (2) or (3). That is, the electric characteristic of the electrode obtained in (1) is improved greatly.

    摘要翻译： 通过AlN缓冲层在蓝宝石衬底上形成GaN层，并掺杂Mg以制备层压体（称为“GaN衬底”）。 通过（1）在GaN衬底被加热到300℃之后或通过（2）气相沉积在GaN衬底留下时，通过（1）气相沉积在GaN衬底上形成50nm厚的金属（Pt和Ni）电极 在室温下。 （3）将（2）得到的电极在氮气氛中加热至300℃。 （1）中获得的电极的接触电阻比在（2）或（3）中获得的电极的接触电阻低两位或三位数。 也就是说，（1）中得到的电极的电特性大大提高。

    Method of fabricating semiconductor interconnections
    7.
    发明授权
    Method of fabricating semiconductor interconnections 失效
    制造半导体互连的方法

    公开(公告)号：US07781339B2

    公开(公告)日：2010-08-24

    申请号：US11765006

    申请日：2007-06-19

    申请人： Takashi Onishi ,  Mikako Takeda ,  Masao Mizuno ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    发明人： Takashi Onishi ,  Mikako Takeda ,  Masao Mizuno ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76864 ,  H01L21/76867

    摘要： A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 μm or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.

    摘要翻译： 提供一种制造半导体互连的方法，其可以形成富Ti层作为阻挡层，并且即使当沟槽具有窄的最小宽度时，也可以将纯Cu材料作为互连材料嵌入设置在绝缘膜中的沟槽的每个角落，并且 很深 该方法可以包括以下步骤：在半导体衬底上的绝缘膜中形成一个或多个凹槽，凹槽具有0.15μm或更小的最小宽度以及凹槽的深度与其最小宽度的比（深度/最小值 宽度）为1以上，沿着形状为10〜50nm的槽的形状，在绝缘膜的槽内形成含有0.5〜10原子％的Ti的Cu合金薄膜，形成纯Cu薄膜 与Cu合金薄膜连接的槽，并使膜在350℃以上退火，使Ti在绝缘膜与Cu合金薄膜之间析出。

    METHOD OF FABRICATING SEMICONDUCTOR INTERCONNECTIONS
    8.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR INTERCONNECTIONS 失效
    制造半导体互连的方法

    公开(公告)号：US20080014743A1

    公开(公告)日：2008-01-17

    申请号：US11765006

    申请日：2007-06-19

    申请人： Takashi Onishi ,  Mikako Takeda ,  Masao Mizuno ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    发明人： Takashi Onishi ,  Mikako Takeda ,  Masao Mizuno ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76843 ,  H01L21/76864 ,  H01L21/76867

    摘要： A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 μm or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.

    摘要翻译： 提供一种制造半导体互连的方法，其可以形成富Ti层作为阻挡层，并且即使当沟槽具有窄的最小宽度时，也可以将纯Cu材料作为互连材料嵌入设置在绝缘膜中的沟槽的每个角落，并且 很深 该方法可以包括以下步骤：在半导体衬底上的绝缘膜中形成一个或多个凹槽，凹槽具有0.15μm或更小的最小宽度以及凹槽的深度与其最小宽度的比（深度/最小值 宽度）为1以上，沿着形状为10〜50nm的槽的形状，在绝缘膜的槽内形成含有0.5〜10原子％的Ti的Cu合金薄膜，形成纯Cu薄膜 与Cu合金薄膜连接的槽，并使膜在350℃以上退火，使Ti在绝缘膜与Cu合金薄膜之间析出。

    FABRICATION METHOD FOR SEMICONDUCTOR INTERCONNECTIONS
    9.
    发明申请
    FABRICATION METHOD FOR SEMICONDUCTOR INTERCONNECTIONS 有权
    半导体互连的制造方法

    公开(公告)号：US20070218690A1

    公开(公告)日：2007-09-20

    申请号：US11532796

    申请日：2006-09-18

    申请人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    发明人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76882 ,  H01L21/76843 ,  H01L21/76867 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.

    摘要翻译： 提供了一种用于互连的制造方法，其能够将铜合金嵌入绝缘膜中的凹部中，并且在绝缘膜和Cu互连之间的界面上形成阻挡层，而不会导致电阻率的上升 当制造嵌入在设置在半导体衬底上的绝缘膜中的凹部中的Cu合金的半导体互连时，互连。 互连的制造方法可以包括以下步骤：形成具有不大于0.15μm的最小宽度的相应凹槽，以及其深度与最小宽度（深度/最小宽度比）的比不小于1，形成 在各凹部中含有0.5〜3原子％的Ti，N为0.4〜2.0原子％的Ti的Cu合金膜，然后将Cu合金膜退火至200℃以上。 并将Cu合金膜加压至50MPa以上，从而将Cu合金膜嵌入各凹部。

    Fabrication method for semiconductor interconnections
    10.
    发明授权
    Fabrication method for semiconductor interconnections 有权
    半导体互连的制造方法

    公开(公告)号：US07538027B2

    公开(公告)日：2009-05-26

    申请号：US11532796

    申请日：2006-09-18

    申请人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    发明人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76882 ,  H01L21/76843 ,  H01L21/76867 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.

    摘要翻译： 提供了一种用于互连的制造方法，其能够将铜合金嵌入绝缘膜中的凹陷中，并且在绝缘膜和Cu互连之间的界面上形成阻挡层，而不会引起电阻率的上升 当制造嵌入在设置在半导体衬底上的绝缘膜中的凹部中的Cu合金的半导体互连时，互连。 互连的制造方法可以包括以下步骤：形成具有不大于0.15μm的最小宽度的相应凹槽，以及其深度与最小宽度（深度/最小宽度比）的比不小于1，形成 在各凹部中含有0.5〜3原子％的Ti，N为0.4〜2.0原子％的Ti的Cu合金膜，然后将Cu合金膜退火至200℃以上。 并将Cu合金膜加压至50MPa以上，从而将Cu合金膜嵌入各凹部。