公开(公告)号：US09167231B2

公开(公告)日：2015-10-20

申请号：US13404562

申请日：2012-02-24

申请人： Tomohisa Kawakami ,  Tsutomu Araki ,  Takeshi Nishikawa ,  Fumihiko Inoue ,  Daigo Shimizu

发明人： Tomohisa Kawakami ,  Tsutomu Araki ,  Takeshi Nishikawa ,  Fumihiko Inoue ,  Daigo Shimizu

IPC分类号： H04N13/02 ,  G06T7/00 ,  H04N13/00

CPC分类号： H04N13/239 ,  H04N13/128 ,  H04N13/189 ,  H04N13/296 ,  H04N2013/0081

摘要： A first temporary taken image taken by a first imaging section of a stereo imaging section, and a second temporary taken image taken by a second imaging section of the stereo imaging section are displayed on a display section. A user aligns the display position of the first temporary taken image with the display position of the second temporary taken image, by moving the first temporary taken image displayed on the display section. Based on the result of the movement, the display positions of two images composing a stereo image taken with the stereo camera are corrected, and the stereo image is displayed on the display section in a stereoscopically visible manner.

摘要翻译： 显示部分显示由立体成像部分的第一成像部分拍摄的第一临时拍摄图像和由立体成像部分的第二成像部分拍摄的第二临时拍摄图像。 通过移动显示在显示部上的第一临时拍摄图像，用户将第一临时拍摄图像的显示位置与第二临时拍摄图像的显示位置对齐。 基于移动的结果，校正由立体摄像机拍摄的构成立体图像的两个图像的显示位置，立体图像以立体视觉的方式显示在显示部分上。

公开(公告)号：US20120218388A1

公开(公告)日：2012-08-30

申请号：US13404562

申请日：2012-02-24

申请人： Tomohisa KAWAKAMI ,  Tsutomu Araki ,  Takeshi Nishikawa ,  Fumihiko Inoue ,  Daigo Shimizu

发明人： Tomohisa KAWAKAMI ,  Tsutomu Araki ,  Takeshi Nishikawa ,  Fumihiko Inoue ,  Daigo Shimizu

IPC分类号： H04N13/02

CPC分类号： H04N13/239 ,  H04N13/128 ,  H04N13/189 ,  H04N13/296 ,  H04N2013/0081

摘要： A first temporary taken image taken by a first imaging section of a stereo imaging section, and a second temporary taken image taken by a second imaging section of the stereo imaging section are displayed on a display section. A user aligns the display position of the first temporary taken image with the display position of the second temporary taken image, by moving the first temporary taken image displayed on the display section. Based on the result of the movement, the display positions of two images composing a stereo image taken with the stereo camera are corrected, and the stereo image is displayed on the display section in a stereoscopically visible manner.

摘要翻译： 显示部分显示由立体成像部分的第一成像部分拍摄的第一临时拍摄图像和由立体成像部分的第二成像部分拍摄的第二临时拍摄图像。 通过移动显示在显示部上的第一临时拍摄图像，用户将第一临时拍摄图像的显示位置与第二临时拍摄图像的显示位置对齐。 基于移动的结果，校正由立体摄像机拍摄的构成立体图像的两个图像的显示位置，立体图像以立体视觉的方式显示在显示部分上。

公开(公告)号：US08669606B2

公开(公告)日：2014-03-11

申请号：US13156766

申请日：2011-06-09

申请人： Fumiaki Toyama ,  Fumihiko Inoue

发明人： Fumiaki Toyama ,  Fumihiko Inoue

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11573

摘要： An embodiment of the invention includes a semiconductor device including a semiconductor substrate with a trench; a tunnel insulating film covering an inner surface of the trench; a trap layer in contact with the tunnel insulating film on an inner surface of an upper portion of the trench; a top insulating film in contact with the trap layer; a gate electrode embedded in the trench, and in contact with the tunnel insulating film at a lower portion of the trench and in contact with the top insulating film at the upper portion of the trench, in which the trap layer and the top insulating film, in between the lower portion of the trench and the upper portion of the trench, extend and protrude from both sides of the trench so as to be embedded in the gate electrode, and a method for manufacturing thereof.

摘要翻译： 本发明的一个实施例包括一种包括具有沟槽的半导体衬底的半导体器件; 覆盖所述沟槽的内表面的隧道绝缘膜; 在所述沟槽的上部的内表面上与所述隧道绝缘膜接触的陷阱层; 与捕获层接触的顶部绝缘膜; 嵌入沟槽中的栅电极，并与沟槽下部的沟道绝缘膜接触并与沟槽上部的顶部绝缘膜接触，其中陷阱层和顶部绝缘膜， 在沟槽的下部和沟槽的上部之间延伸并从沟槽的两侧突出以便嵌入栅极中，以及其制造方法。

公开(公告)号：US08318566B2

公开(公告)日：2012-11-27

申请号：US13156122

申请日：2011-06-08

申请人： Fumihiko Inoue ,  Haruki Souma ,  Yukio Hayakawa

发明人： Fumihiko Inoue ,  Haruki Souma ,  Yukio Hayakawa

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/11565

摘要： Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.

摘要翻译： 公开了用于隔离半导体器件中的相邻电荷累积层的装置和方法。 在一个实施例中，半导体器件包括形成在半导体衬底中的位线，形成在半导体衬底上的电荷累积层，形成在位线上的电荷累积层上的字线和形成在半导体衬底中的沟道区 在字线之下以及位线和其相邻位线之间。 对于半导体器件，电荷累积层形成在字线的宽度方向上的沟道区上方，并且字线的宽度被设定为比沟道区的端部与中心部的距离更窄 在字线的长度方向上的通道区域。

公开(公告)号：US09263249B2

公开(公告)日：2016-02-16

申请号：US12166290

申请日：2008-07-01

申请人： Watanabe Tomohiro ,  Fumihiko Inoue

发明人： Watanabe Tomohiro ,  Fumihiko Inoue

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/28 ,  H01L21/67 ,  H01L21/02 ,  H01L29/792

CPC分类号： H01L21/02057 ,  H01L21/28282 ,  H01L21/67028 ,  H01L29/7923

摘要： The present invention is directed to a method and an apparatus for manufacturing a semiconductor device including step S22 to form an insulating film on a front surface of a semiconductor wafer that is a surface on which a semiconductor element is to be formed and on a back surface that is a surface opposing the front surface, step S26 to remove the insulating film formed on the back surface by selectively providing a first chemical on the back surface of the semiconductor wafer, and step S30 to remove the insulating film formed on the front surface by simultaneously immersing the plurality of semiconductor wafers in a second chemical.

摘要翻译： 本发明涉及一种用于制造半导体器件的方法和装置，包括步骤S22以在半导体晶片的正面上形成绝缘膜，半导体晶片是要形成半导体元件的表面和背面 即与前表面相对的表面，步骤S26通过在半导体晶片的背面上选择性地提供第一化学物质来除去形成在背面上的绝缘膜，以及步骤S30，通过以下步骤除去形成在前表面上的绝缘膜： 同时将多个半导体晶片浸入第二种化学品中。

公开(公告)号：US08895405B2

公开(公告)日：2014-11-25

申请号：US11963415

申请日：2007-12-21

申请人： Fumihiko Inoue ,  Yukio Hayakawa

发明人： Fumihiko Inoue ,  Yukio Hayakawa

IPC分类号： H01L21/76 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76224 ,  H01L21/3086

摘要： A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成具有开口部分的氮化硅膜，在氮化硅膜上和在开口部分的侧面上形成氧化硅膜，对氧化硅进行蚀刻处理 膜，使得在开口部分的侧面上形成侧壁，利用侧壁和氮化硅膜作为掩模在半导体衬底上形成沟槽，并在沟槽中形成绝缘层。 形成氧化硅膜的步骤包括用等离子体氧化法或自由基氧化法氧化氮化硅膜。

公开(公告)号：US06602771B2

公开(公告)日：2003-08-05

申请号：US09939639

申请日：2001-08-28

申请人： Fumihiko Inoue ,  Masayuki Tanaka

发明人： Fumihiko Inoue ,  Masayuki Tanaka

IPC分类号： H01L213205

CPC分类号： H01L21/823842 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/6659

摘要： The method for fabricating the semiconductor device comprises the step of: forming a gate insulation film 14 on a semiconductor substrate 10; forming a semiconductor layer 22 containing boron on the gate insulation film 14; forming a silicon nitride film 28 having an Si—H bond concentration in the film immediately after deposited which is below 4.3×1020 cm−3 measured by FT-IR; and patterning the silicon nitride film 28 and the semiconductor layer 22 to form a gate electrode 30 of a semiconductor layer 22 having the upper surface covered by the silicon nitride film 28. Whereby the release of hydrogen in the films in the thermal processing after the silicon nitride film has been formed can be decreased, and the boron penetration from the p-type gate electrode 30p can be suppressed.

公开(公告)号：US08552523B2

公开(公告)日：2013-10-08

申请号：US13206380

申请日：2011-08-09

申请人： Fumiaki Toyama ,  Fumihiko Inoue

发明人： Fumiaki Toyama ,  Fumihiko Inoue

IPC分类号： H01L21/70

CPC分类号： H01L27/11565 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括形成在半导体衬底上沿第一方向延伸的浅沟槽隔离（STI）区域，形成在半导体衬底上沿与第一方向相交的第二方向延伸的掩模层，并在半导体衬底上形成沟槽，并通过 使用STI区域和掩模层作为掩模。 此外，该方法包括形成电荷存储层以覆盖沟槽并在沟槽和掩模层的侧表面上形成导电层。 字线由通过蚀刻在第一方向相对的沟槽的侧表面上的导电层形成。 字线彼此分离并在第二方向上延伸。

公开(公告)号：US07994007B2

公开(公告)日：2011-08-09

申请号：US12337461

申请日：2008-12-17

申请人： Fumiaki Toyama ,  Fumihiko Inoue

发明人： Fumiaki Toyama ,  Fumihiko Inoue

IPC分类号： H01L21/336

CPC分类号： H01L27/11565 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括形成在半导体衬底上沿第一方向延伸的浅沟槽隔离（STI）区域，形成在半导体衬底上沿与第一方向相交的第二方向延伸的掩模层，并在半导体衬底上形成沟槽，并通过 使用STI区域和掩模层作为掩模。 此外，该方法包括形成电荷存储层以覆盖沟槽并在沟槽和掩模层的侧表面上形成导电层。 字线由通过蚀刻在第一方向相对的沟槽的侧表面上的导电层形成。 字线彼此分离并在第二方向上延伸。

公开(公告)号：US07981746B2

公开(公告)日：2011-07-19

申请号：US12341874

申请日：2008-12-22

申请人： Fumiaki Toyama ,  Fumihiko Inoue

发明人： Fumiaki Toyama ,  Fumihiko Inoue

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11573

摘要： The present invention provides a semiconductor device including a semiconductor substrate provided with a trench section; a tunnel insulating film covering an inner surface of the trench section; a trap layer provided in contact with the tunnel insulating film on an inner surface of an upper portion of the trench section; a top insulating film provided in contact with the trap layer; a gate electrode embedded in the trench section, and provided in contact with the tunnel insulating film at a lower portion of the trench section and in contact with the top insulating film at the upper portion of the trench section, in which the trap layer and the top insulating film, in between the lower portion of the trench section and the upper portion of the trench section, extend and protrude from both sides of the trench section so as to be embedded in the gate electrode, and a method for manufacturing thereof.

摘要翻译： 本发明提供一种半导体器件，其包括设置有沟槽部分的半导体衬底; 覆盖所述沟槽部的内表面的隧道绝缘膜; 在所述沟槽部的上部的内表面上设置与所述隧道绝缘膜接触的陷阱层; 设置成与所述捕获层接触的顶部绝缘膜; 栅电极，其嵌入在沟槽部中，并且与沟道绝缘膜在沟槽部的下部接触并与沟槽部的上部的顶部绝缘膜接触而设置，其中阱层和 在沟槽部分的下部和沟槽部分的上部之间的顶部绝缘膜从沟槽部分的两侧延伸并突出以嵌入在栅电极中，以及其制造方法。