公开(公告)号：US06310806B1

公开(公告)日：2001-10-30

申请号：US09716322

申请日：2000-11-21

申请人： Tomoki Higashi ,  Hiroaki Nakano

发明人： Tomoki Higashi ,  Hiroaki Nakano

IPC分类号： G11C700

CPC分类号： G11C29/84

摘要： A redundant memory circuit stores a defective row address. A switch circuit connects a spare row decoder with the wire for transmitting a row address signal according to the defective row address stored in the redundant memory circuit when the power supply is turned on. A row decoder deactivating circuit, when the power supply is turned on, deactivates the part of the row decoder corresponding to the defective row address according to the defective row address stored in the redundant memory circuit. As a result, when the row address buffer outputs the row address signal corresponding to the defective row address, the spare row decoder decodes the row address signal, thereby selecting a spare word line immediately.

摘要翻译： 冗余存储器电路存储有缺陷的行地址。 当电源接通时，开关电路根据存储在冗余存储器电路中的有缺陷的行地址，将备用行解码器与用于发送行地址信号的布线相连接。 行解码器去激活电路，当电源接通时，根据存储在冗余存储器电路中的有缺陷的行地址，去激活对应于有缺陷行地址的行解码器的部分。 结果，当行地址缓冲器输出与缺陷行地址对应的行地址信号时，备用行解码器解码行地址信号，从而立即选择备用字线。

公开(公告)号：US20080205181A1

公开(公告)日：2008-08-28

申请号：US12099647

申请日：2008-04-08

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4099 ,  G11C2211/4016

摘要： A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line.

摘要翻译： 半导体存储装置包括信息存储单元，数据可写入到其中，或从哪个数据可以读取; 包括以矩阵排列的信息存储单元的存储单元阵列; 连接到存储单元阵列的行中的信息存储单元的信息字线; 连接到存储单元阵列的列中的信息存储单元的信息位线; 存储单一数字数据以产生用于区分存储在信息存储单元中的数据的参考电位的参考存储单元; 连接到参考存储单元的参考位线; 以及连接到信息位线和参考位线的读出放大器。

公开(公告)号：US07139216B2

公开(公告)日：2006-11-21

申请号：US10864632

申请日：2004-06-10

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C8/00 ,  G11C11/34

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： A semiconductor storage device includes memory cells having a floating body region and storing data by accumulating or releasing electric charges in or from the floating body region; a memory cell array including a matrix arrangement of the memory cells; a plurality of word lines each connected to the memory cells of each row in the memory cell array; and a counter cell array including counter cells each provided in correspondence to each word line to store occurrences of activation of the word line to read out data from the memory cells.

摘要翻译： 半导体存储装置包括具有浮体区域的存储单元，并且通过在浮体区域中积聚或释放电荷来存储数据; 存储单元阵列，包括存储单元的矩阵排列; 多个字线，各自连接到存储单元阵列中的每一行的存储单元; 以及包括对应单元的计数单元阵列，每个单元对应于每个字线设置以存储字线的激活以从存储器单元读出数据的发生。

公开(公告)号：US06724653B1

公开(公告)日：2004-04-20

申请号：US10160058

申请日：2002-06-04

申请人： Yoshihisa Iwata ,  Tomoki Higashi

发明人： Yoshihisa Iwata ,  Tomoki Higashi

IPC分类号： G11C1100

CPC分类号： G11C11/16 ,  G11C8/10

摘要： A read block is constituted of a plurality of TMR elements arranged in a lateral direction. One end of each of the TMR elements in the read block is connected in common, and connected to a source line via a read select switch. The other ends of TMR elements are independently connected to read bit lines/write word lines. The read bit lines/write word lines are connected to common data lines via a row select switch. The common data lines are connected to a read circuit.

摘要翻译： 读块由沿横向布置的多个TMR元件构成。 读块中的每个TMR元件的一端被共同连接，并通过读选择开关连接到源极线。 TMR元件的另一端独立地连接到读位线/写字线。 读取位线/写入字线通过行选择开关连接到公共数据线。 公共数据线连接到读取电路。

公开(公告)号：US08493796B2

公开(公告)日：2013-07-23

申请号：US13239490

申请日：2011-09-22

申请人： Tomoki Higashi ,  Kazumi Tanimoto

发明人： Tomoki Higashi ,  Kazumi Tanimoto

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621

摘要： A nonvolatile semiconductor memory device according to an embodiment of the present invention includes: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells having a charge storage layer and a control electrode; and a control unit configured to execute a write cycle multiple times, the write cycle including a write operation and a write verify operation, the write operation being an operation for applying a write pulse voltage multiple times to the control electrode selected for data write, and the write verify operation being an operation for determining whether data write is completed or not. During one time of the write operation, the control unit makes a voltage value of a finally applied write pulse voltage larger than a voltage value of an initially applied write pulse voltage.

摘要翻译： 根据本发明实施例的非易失性半导体存储器件包括：存储单元阵列，其中布置有多个存储单元，每个存储单元具有电荷存储层和控制电极; 以及控制单元，被配置为执行多次写入周期，所述写入周期包括写入操作和写入验证操作，所述写入操作是用于将多个写入脉冲电压施加到被选择用于数据写入的控制电极的操作，以及 写入验证操作是用于确定数据写入是否完成的操作。 在写入操作的一个时间期间，控制单元使最终施加的写入脉冲电压的电压值大于初始施加的写入脉冲电压的电压值。

公开(公告)号：US20080165558A1

公开(公告)日：2008-07-10

申请号：US11873020

申请日：2007-10-16

申请人： Katsuyuki Fujita ,  Tomoki Higashi

发明人： Katsuyuki Fujita ,  Tomoki Higashi

IPC分类号： G11C5/06 ,  G11C7/02

CPC分类号： G11C11/4097 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A semiconductor memory device has memory cells each of which has a MIS type of transistor capable of setting one of two kinds of threshold potentials, reference cells used for determining data stored in the memory cells, which have the same size, shape and electrical properties as those of the memory cells, word lines connected to gates of the memory cells, reference word lines connected to gates of the reference cells, source line contacts connected to sources of the memory cells and the reference cells, and bit line contacts connected to drains of the memory cells and the reference cells, arrangement order of the source line contact, the word line and bit line contact connected to each of the memory cells is equal to arrangement order of the source line contact, the reference word line and the bit line contact connected to the reference cell corresponding to the memory cell.

摘要翻译： 半导体存储器件具有存储单元，每个存储单元具有能够设置两种阈值电位之一的MIS型晶体管，用于确定存储在存储单元中的数据的参考单元，其尺寸，形状和电特性与 连接到存储单元的栅极的连接到参考单元的栅极的参考字线，连接到存储单元的源极和参考单元的源极线触点以及连接到存储单元的漏极的位线触点 存储单元和参考单元，源极线接触的排列顺序，连接到每个存储单元的字线和位线接触等于源极线接触，参考字线和位线接触的排列顺序 连接到与存储器单元相对应的参考单元。

公开(公告)号：US07126843B2

公开(公告)日：2006-10-24

申请号：US10214568

申请日：2002-08-09

申请人： Tomoki Higashi

发明人： Tomoki Higashi

IPC分类号： G11C11/00

CPC分类号： G11C11/15

摘要： A semiconductor memory device includes memory cell arrays, word lines, sub-sense lines, main sense line, row decoders, column decoders, first switch elements, read circuit, and write circuit. Each memory cell array has a matrix of memory cells including magnetoresistive elements. Each magnetoresistive element has first and second magnetic layers and a first insulating layer formed between the first and second magnetic layers. The word line is connected to the first magnetic layers on each row. The sub-sense line is connected to the second magnetic layers on each column. The main sense line is connected to each sub-sense line. The row decoder and column decoder select a word line and sub-sense line. The first switch element connects the sub-sense line selected by the column decoder to the main sense line. The read circuit reads out data from a memory cell. The write circuit writes data in a memory cell.

公开(公告)号：US07095652B2

公开(公告)日：2006-08-22

申请号：US11049727

申请日：2005-02-04

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C11/34

CPC分类号： G11C11/404 ,  G11C11/4094 ,  G11C29/50 ,  G11C2211/4016

摘要： A semiconductor storage device comprises memory cells that store data by accumulating or releasing an electric charge; a memory cell array having a matrix arrangement of the memory cells; a plurality of word lines connected to memory cells aligned on rows of the memory cell array; a plurality of sub-bit lines connected to memory cells aligned on columns of the memory cell array; a bit line select circuit selecting the sub-bit line of a column; a main bit line connected to the sub-bit line selected by the bit line select circuit; a sense line detecting the potential of the sub-bit line selected by the bit line select circuit via the main bit line and reading data out of the memory cell; a write driver applying a voltage to the sub-bit line selected by the bit line select circuit via the main bit line and writing data into the memory cell; and a first switching element connected to the main bit line and turning on when the current flowing in the memory cell is detected externally via the sub-bit line without the use of the sense line or when a voltage is applied to the memory cell externally via the sub-bit line without the use of the write driver.

摘要翻译： 半导体存储装置包括通过累积或释放电荷来存储数据的存储单元; 具有所述存储单元的矩阵排列的存储单元阵列; 连接到与存储单元阵列的行对齐的存储单元的多个字线; 连接到与存储单元阵列的列对齐的存储单元的多个子位线; 选择列的子位线的位线选择电路; 连接到由位线选择电路选择的子位线的主位线; 感测线通过主位线检测由位线选择电路选择的子位线的电位，并从存储器单元读出数据; 写入驱动器，通过主位线向位线选择电路选择的子位线施加电压，并将数据写入存储单元; 以及连接到主位线的第一开关元件，并且在不使用感测线的情况下经由子位线从外部检测在存储单元中流动的电流时，或者当外部经由电压施加到存储器单元时，导通 子位线不使用写驱动。

公开(公告)号：US06862210B2

公开(公告)日：2005-03-01

申请号：US10422971

申请日：2003-04-25

申请人： Kenji Tsuchida ,  Yoshihisa Iwata ,  Tomoki Higashi

发明人： Kenji Tsuchida ,  Yoshihisa Iwata ,  Tomoki Higashi

IPC分类号： G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/00

CPC分类号： G11C11/15

摘要： A memory cell comprises a magneto-resistive element of which electrical resistance value varies with magnetism. A sub-bit line is connected to one end of the memory cell. A main-bit line is connected to the sub-bit line via a first selection circuit. A sense-amplifier is connected to the main-bit line via a second selection circuit. A wiring line is connected to the other end of the memory cell and arranged in a first direction. A first operation circuit is connected to one end of the wiring line via a third selection circuit. A second operation circuit is connected to the other end of the wiring line. A word line passes over an intersection between the memory cell and the wiring line and is arranged in a second direction perpendicular to the first direction.

摘要翻译： 存储单元包括电阻值随磁力而变化的磁阻元件。 子位线连接到存储单元的一端。 主位线经由第一选择电路连接到子位线。 读出放大器经由第二选择电路连接到主位线。 布线沿着第一方向与存储单元的另一端连接。 第一操作电路经由第三选择电路连接到布线的一端。 第二操作电路连接到布线的另一端。 字线通过存储单元和布线之间的交叉点，并且布置在垂直于第一方向的第二方向上。

公开(公告)号：US20050036376A1

公开(公告)日：2005-02-17

申请号：US10945139

申请日：2004-09-21

申请人： Yoshihisa Iwata ,  Tomoki Higashi

发明人： Yoshihisa Iwata ,  Tomoki Higashi

IPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/00

CPC分类号： G11C11/16 ,  G11C11/15

摘要： TMR elements are arranged at the intersections between word lines and bit lines. One end of each word line is connected to the ground point through a row select switch. One end of each bit line is connected to a bit line bias circuit. In read operation, the bit line bias circuit applies a bias potential to all the bit lines. The selected word line is short-circuited to the ground point. Unselected word lines are set in a floating state.

摘要翻译： TMR元件布置在字线和位线之间的交点处。 每个字线的一端通过行选择开关连接到地面点。 每个位线的一端连接到位线偏置电路。 在读操作中，位线偏置电路向所有位线施加偏置电位。 所选字线短路到地面点。 未选择的字线设置为浮动状态。