公开(公告)号：US20080251830A1

公开(公告)日：2008-10-16

申请号：US12060522

申请日：2008-04-01

申请人： Tomoki Higashi ,  Takashi Ohsawa ,  Ryo Fukuda

发明人： Tomoki Higashi ,  Takashi Ohsawa ,  Ryo Fukuda

IPC分类号： H01L27/102 ,  G11C16/04

CPC分类号： H01L27/1022 ,  G11C11/4023 ,  G11C11/4026 ,  G11C11/405 ,  G11C11/4085 ,  G11C2211/4016 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.

摘要翻译： 本公开涉及一种半导体存储装置，其包括设置在设置在半导体衬底上的绝缘层上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的主体，所述主体处于电浮动状态; 与源极层接触的发射极层，发射极层与源极层具有相反的导电类型; 包括源层，漏极层和主体的字线，字线被提供给在多个维度上排列的存储单元中沿第一方向排列的存储单元; 连接到沿着第一方向排列的存储单元的源层的源极线; 以及连接到沿与第一方向相交的第二方向排列的存储单元的漏极层的位线。

公开(公告)号：US07893478B2

公开(公告)日：2011-02-22

申请号：US12060522

申请日：2008-04-01

申请人： Tomoki Higashi ,  Takashi Ohsawa ,  Ryo Fukuda

发明人： Tomoki Higashi ,  Takashi Ohsawa ,  Ryo Fukuda

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L23/52 ,  H01L21/70 ,  H01L29/66

CPC分类号： H01L27/1022 ,  G11C11/4023 ,  G11C11/4026 ,  G11C11/405 ,  G11C11/4085 ,  G11C2211/4016 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.

摘要翻译： 本公开涉及一种半导体存储装置，其包括设置在设置在半导体衬底上的绝缘层上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的主体，所述主体处于电浮动状态; 与源极层接触的发射极层，发射极层与源极层具有相反的导电类型; 包括源层，漏极层和主体的字线，字线被提供给在多个维度上排列的存储单元中沿第一方向排列的存储单元; 连接到沿着第一方向排列的存储单元的源层的源极线; 以及连接到沿与第一方向相交的第二方向排列的存储单元的漏极层的位线。

公开(公告)号：US20080205181A1

公开(公告)日：2008-08-28

申请号：US12099647

申请日：2008-04-08

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4099 ,  G11C2211/4016

摘要： A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line.

摘要翻译： 半导体存储装置包括信息存储单元，数据可写入到其中，或从哪个数据可以读取; 包括以矩阵排列的信息存储单元的存储单元阵列; 连接到存储单元阵列的行中的信息存储单元的信息字线; 连接到存储单元阵列的列中的信息存储单元的信息位线; 存储单一数字数据以产生用于区分存储在信息存储单元中的数据的参考电位的参考存储单元; 连接到参考存储单元的参考位线; 以及连接到信息位线和参考位线的读出放大器。

公开(公告)号：US07139216B2

公开(公告)日：2006-11-21

申请号：US10864632

申请日：2004-06-10

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C8/00 ,  G11C11/34

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： A semiconductor storage device includes memory cells having a floating body region and storing data by accumulating or releasing electric charges in or from the floating body region; a memory cell array including a matrix arrangement of the memory cells; a plurality of word lines each connected to the memory cells of each row in the memory cell array; and a counter cell array including counter cells each provided in correspondence to each word line to store occurrences of activation of the word line to read out data from the memory cells.

摘要翻译： 半导体存储装置包括具有浮体区域的存储单元，并且通过在浮体区域中积聚或释放电荷来存储数据; 存储单元阵列，包括存储单元的矩阵排列; 多个字线，各自连接到存储单元阵列中的每一行的存储单元; 以及包括对应单元的计数单元阵列，每个单元对应于每个字线设置以存储字线的激活以从存储器单元读出数据的发生。

公开(公告)号：US07095652B2

公开(公告)日：2006-08-22

申请号：US11049727

申请日：2005-02-04

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C11/34

CPC分类号： G11C11/404 ,  G11C11/4094 ,  G11C29/50 ,  G11C2211/4016

摘要： A semiconductor storage device comprises memory cells that store data by accumulating or releasing an electric charge; a memory cell array having a matrix arrangement of the memory cells; a plurality of word lines connected to memory cells aligned on rows of the memory cell array; a plurality of sub-bit lines connected to memory cells aligned on columns of the memory cell array; a bit line select circuit selecting the sub-bit line of a column; a main bit line connected to the sub-bit line selected by the bit line select circuit; a sense line detecting the potential of the sub-bit line selected by the bit line select circuit via the main bit line and reading data out of the memory cell; a write driver applying a voltage to the sub-bit line selected by the bit line select circuit via the main bit line and writing data into the memory cell; and a first switching element connected to the main bit line and turning on when the current flowing in the memory cell is detected externally via the sub-bit line without the use of the sense line or when a voltage is applied to the memory cell externally via the sub-bit line without the use of the write driver.

摘要翻译： 半导体存储装置包括通过累积或释放电荷来存储数据的存储单元; 具有所述存储单元的矩阵排列的存储单元阵列; 连接到与存储单元阵列的行对齐的存储单元的多个字线; 连接到与存储单元阵列的列对齐的存储单元的多个子位线; 选择列的子位线的位线选择电路; 连接到由位线选择电路选择的子位线的主位线; 感测线通过主位线检测由位线选择电路选择的子位线的电位，并从存储器单元读出数据; 写入驱动器，通过主位线向位线选择电路选择的子位线施加电压，并将数据写入存储单元; 以及连接到主位线的第一开关元件，并且在不使用感测线的情况下经由子位线从外部检测在存储单元中流动的电流时，或者当外部经由电压施加到存储器单元时，导通 子位线不使用写驱动。

公开(公告)号：US07839711B2

公开(公告)日：2010-11-23

申请号：US12352876

申请日：2009-01-13

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C7/00

CPC分类号： G11C11/404 ,  G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065 ,  G11C2211/4068

摘要： A memory including; cells, wherein a refresh operation includes a first refresh and a second refresh, in the first refresh, a first potential higher than a gate potential in a retention is applied to the gate in a state having a source potential applied to the drain, and thereafter the gate potential in the retention is applied to the gate, thereby a first current passes to the cell, and in the second refresh, a second potential higher than a gate potential in the retention is applied to the gate, and a third potential higher than the gate potential in the retention is applied to the drain, thereby a second current passes to the cell, and a state of the cell is shifted to an equilibrium state in which amounts of the first and the second currents flowing during one cycle becomes substantially equal.

摘要翻译： 一个记忆包括 单元，其中刷新操作包括第一刷新和第二刷新，在具有施加到漏极的源极电位的状态下，将高于保持中的栅极电位的第一电位施加到栅极，之后 将保持中的栅极电位施加到栅极，由此第一电流流到电池，并且在第二次刷新中，将高于保持时的栅极电位的第二电位施加到栅极，并且第三电位高于 保留中的栅极电位被施加到漏极，由此第二电流流到电池，并且电池的状态转移到平衡状态，其中在一个周期期间流动的第一和第二电流的量变得基本相等 。

公开(公告)号：US07839699B2

公开(公告)日：2010-11-23

申请号：US12050386

申请日：2008-03-18

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C7/00 ,  G11C7/02 ,  G11C5/14

CPC分类号： H01L29/7841 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C11/404 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5006 ,  G11C2211/4016

摘要： This disclosure concerns a semiconductor memory device comprising: a memory cell array having memory cells arrayed two-dimensionally; word lines connected to the memory cells of rows of the memory cell array; bit lines connected to the memory cells of columns of the memory cell array; sense amplifiers connected to the bit lines, and detecting data stored in the memory cells; a test pad passing a predetermined reference current from a power source, and transmitting a reference voltage based on the reference current; and test circuits connected between the power source and the test pad and intervening between the power source and the bit lines, the test circuits passing test currents according to the reference voltage via the bit lines.

摘要翻译： 本公开涉及一种半导体存储器件，包括：具有二维排列的存储单元的存储单元阵列; 连接到存储单元阵列的行的存储单元的字线; 连接到存储单元阵列的列的存储单元的位线; 连接到位线的感测放大器，以及检测存储在存储单元中的数据; 测试垫，其从电源通过预定的参考电流，并且基于所述参考电流传输参考电压; 以及连接在电源和测试焊盘之间并且插入电源和位线之间的测试电路，测试电路经由位线根据参考电压使测试电流通过。

公开(公告)号：US20070109844A1

公开(公告)日：2007-05-17

申请号：US11476878

申请日：2006-06-29

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C7/065 ,  G11C7/08 ,  G11C8/10 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2211/4016

摘要： A semiconductor memory device includes a memory cell including a floating body region in an electrically floating state and storing data by accumulating or discharging charges in or from the floating body region; a memory cell array including a plurality of the memory cells; a word line connected to a gate of the memory cell; a bit line connected to a diffusion layer of the memory cell; a sense amplifier connected to the bit line; and a decoder applying a first potential to the word line when data “1” is written to the memory cell and applying a second potential different from the first potential to the word line when data “0” is written to the memory cell.

摘要翻译： 半导体存储器件包括：存储单元，其包括处于浮动状态的浮动体区域，并且通过在浮体区域中积聚或排出电荷来存储数据; 包括多个存储单元的存储单元阵列; 连接到存储单元的门的字线; 连接到存储单元的扩散层的位线; 连接到位线的读出放大器; 以及解码器，当数据“1”被写入存储单元时向字线施加第一电位，并且当数据“0”被写入到存储单元时，将与第一电位不同的第二电位施加到字线。

公开(公告)号：US07463541B2

公开(公告)日：2008-12-09

申请号：US12099647

申请日：2008-04-08

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4099 ,  G11C2211/4016

摘要： A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line.

摘要翻译： 半导体存储装置包括信息存储单元，数据可以被写入其中，或从哪个数据可以被读取; 包括以矩阵排列的信息存储单元的存储单元阵列; 连接到存储单元阵列的行中的信息存储单元的信息字线; 连接到存储单元阵列的列中的信息存储单元的信息位线; 存储单一数字数据以产生用于区分存储在信息存储单元中的数据的参考电位的参考存储单元; 连接到参考存储单元的参考位线; 以及连接到信息位线和参考位线的读出放大器。

公开(公告)号：US20060023540A1

公开(公告)日：2006-02-02

申请号：US11049727

申请日：2005-02-04

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4094 ,  G11C29/50 ,  G11C2211/4016

摘要： A semiconductor storage device comprises memory cells that store data by accumulating or releasing an electric charge; a memory cell array having a matrix arrangement of the memory cells; a plurality of word lines connected to memory cells aligned on rows of the memory cell array; a plurality of sub-bit lines connected to memory cells aligned on columns of the memory cell array; a bit line select circuit selecting the sub-bit line of a column; a main bit line connected to the sub-bit line selected by the bit line select circuit; a sense line detecting the potential of the sub-bit line selected by the bit line select circuit via the main bit line and reading data out of the memory cell; a write driver applying a voltage to the sub-bit line selected by the bit line select circuit via the main bit line and writing data into the memory cell; and a first switching element connected to the main bit line and turning on when the current flowing in the memory cell is detected externally via the sub-bit line without the use of the sense line or when a voltage is applied to the memory cell externally via the sub-bit line without the use of the write driver.