公开(公告)号：US20080185639A1

公开(公告)日：2008-08-07

申请号：US12027655

申请日：2008-02-07

申请人： Tomomitsu Risaki ,  Jun Osanai

发明人： Tomomitsu Risaki ,  Jun Osanai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/785

摘要： Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

摘要翻译： 沟槽部分（10）形成在井（5）中，以便在井（5）中提供不均匀性。 在沟槽部分（10）的上表面和内部经由绝缘膜（7）形成栅电极（2）。 源极区域（3）以栅极长度方向形成在栅电极（2）的一侧，而另一侧的漏极区域（4）形成。 源极区域（3）和漏极区域（4）都形成为靠近栅电极（2）的底部附近。 通过深深地形成源极区域（3）和漏极区域（4），电流均匀地流过整个沟槽部分（10），并且在阱（5）中形成的凹凸增加了有效栅极宽度以降低导通电阻 并提高其驱动能力。

公开(公告)号：US08803231B2

公开(公告)日：2014-08-12

申请号：US13438058

申请日：2012-04-03

申请人： Tomomitsu Risaki ,  Jun Osanai

发明人： Tomomitsu Risaki ,  Jun Osanai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/785

摘要： Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increases the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

摘要翻译： 沟槽部分（10）形成在井（5）中，以便在井（5）中提供不均匀性。 在沟槽部分（10）的上表面和内部经由绝缘膜（7）形成栅电极（2）。 源极区域（3）以栅极长度方向形成在栅电极（2）的一侧，而另一侧的漏极区域（4）形成。 源极区域（3）和漏极区域（4）都形成为靠近栅电极（2）的底部附近。 通过深深地形成源极区域（3）和漏极区域（4），电流均匀地流过整个沟槽部分（10），并且在阱（5）中形成的凹凸增加了有效栅极宽度以降低导通电阻 并提高其驱动能力。

公开(公告)号：US08168494B2

公开(公告)日：2012-05-01

申请号：US12027655

申请日：2008-02-07

申请人： Tomomitsu Risaki ,  Jun Osanai

发明人： Tomomitsu Risaki ,  Jun Osanai

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/785

摘要： Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

摘要翻译： 沟槽部分（10）形成在井（5）中，以便在井（5）中提供不均匀性。 在沟槽部分（10）的上表面和内部经由绝缘膜（7）形成栅电极（2）。 源极区域（3）以栅极长度方向形成在栅电极（2）的一侧，而另一侧的漏极区域（4）形成。 源极区域（3）和漏极区域（4）都形成为靠近栅电极（2）的底部附近。 通过深深地形成源极区域（3）和漏极区域（4），电流均匀地流过整个沟槽部分（10），并且在阱（5）中形成的凹凸增加了有效栅极宽度以降低导通电阻 并提高其驱动能力。

公开(公告)号：US20120187476A1

公开(公告)日：2012-07-26

申请号：US13438058

申请日：2012-04-03

申请人： Tomomitsu Risaki ,  Jun Osanai

发明人： Tomomitsu Risaki ,  Jun Osanai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/785

摘要： Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

摘要翻译： 沟槽部分（10）形成在井（5）中，以便在井（5）中提供不均匀性。 在沟槽部分（10）的上表面和内部经由绝缘膜（7）形成栅电极（2）。 源极区域（3）以栅极长度方向形成在栅电极（2）的一侧，而另一侧的漏极区域（4）形成。 源极区域（3）和漏极区域（4）都形成为靠近栅电极（2）的底部附近。 通过深深地形成源极区域（3）和漏极区域（4），电流均匀地流过整个沟槽部分（10），并且在阱（5）中形成的凹凸增加了有效栅极宽度以降低导通电阻 并提高其驱动能力。

公开(公告)号：US08071460B2

公开(公告)日：2011-12-06

申请号：US12315636

申请日：2008-12-04

申请人： Tomomitsu Risaki ,  Jun Osanai

发明人： Tomomitsu Risaki ,  Jun Osanai

IPC分类号： H01L21/76 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3065 ,  H01L22/26

摘要： In a method of manufacturing a semiconductor device, a first film is formed directly on a semiconductor substrate and a second film is formed on the first film. A region of the second film is then etched to form an opening that exposes the first film. The first film is then arbitrarily patterned by etching to expose a surface of the semiconductor substrate. Thereafter, the second film and the exposed surface of the semiconductor substrate are simultaneously etched using the patterned first film as a mask and in an etching ambient having a low etching rate for the first film and having a high etching rate for the second film and the semiconductor substrate until the second film is almost completely etched and a detection amount of a monitored element of the first film increases.

摘要翻译： 在制造半导体器件的方法中，第一膜直接形成在半导体衬底上，第二膜形成在第一膜上。 然后蚀刻第二膜的区域以形成暴露第一膜的开口。 然后通过蚀刻来任意地构图第一膜以暴露半导体衬底的表面。 此后，使用图案化的第一膜作为掩模，并且在对于第一膜具有低蚀刻速率的蚀刻环境中并且对于第二膜具有高蚀刻速率的同时蚀刻第二膜和半导体基板的暴露表面，并且 半导体衬底，直到第二膜几乎被完全蚀刻，并且第一膜的监测元件的检测量增加。

公开(公告)号：US20090156009A1

公开(公告)日：2009-06-18

申请号：US12315636

申请日：2008-12-04

申请人： Tomomitsu Risaki ,  Jun Osanai

发明人： Tomomitsu Risaki ,  Jun Osanai

IPC分类号： H01L21/314

CPC分类号： H01L21/3065 ,  H01L22/26

摘要： Provided is a method of manufacturing a semiconductor device capable of providing a stable trench depth, including: forming, on a semiconductor substrate, a first film having a high etching selectivity with respect to the semiconductor substrate; forming, on the first film, a second film having a high etching selectivity with respect to the first film; etching a region of a part of the second film and the first film to expose a surface of the semiconductor substrate in the region; and etching the exposed surface of the semiconductor substrate to form a trench.

摘要翻译： 提供一种能够提供稳定的沟槽深度的半导体器件的制造方法，包括：在半导体衬底上形成相对于半导体衬底具有高蚀刻选择性的第一膜; 在第一膜上形成相对于第一膜具有高蚀刻选择性的第二膜; 蚀刻第二膜的一部分的区域和第一膜，以暴露该区域中的半导体衬底的表面; 并蚀刻半导体衬底的暴露表面以形成沟槽。

公开(公告)号：US08760926B2

公开(公告)日：2014-06-24

申请号：US13534132

申请日：2012-06-27

申请人： Jun Osanai ,  Yoshitsugu Hirose ,  Kazuhiro Tsumura ,  Ayako Inoue

发明人： Jun Osanai ,  Yoshitsugu Hirose ,  Kazuhiro Tsumura ,  Ayako Inoue

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0441 ,  G11C16/26

摘要： Provided is a memory circuit in which erroneous writing is less likely to occur at the time of power-on. A memory circuit (10) includes: a P-channel non-volatile memory element (15) for writing, to which a voltage is applied between a source and a drain thereof only during writing so as to write data; and an N-channel non-volatile memory element (16) for reading, which has a control gate and a floating gate provided in common to a control gate and a floating gate of the P-channel non-volatile memory element (15) and to which a voltage is applied to a source and a drain thereof only during reading so as to read the data.

摘要翻译： 提供了在上电时不太可能发生错误写入的存储电路。 存储器电路（10）包括：用于写入的P沟道非易失性存储元件（15），仅在写入期间在其源极和漏极之间施加电压以便写入数据; 和用于读取的N沟道非易失性存储器元件（16），其具有与P沟道非易失性存储元件（15）的控制栅极和浮置栅极共同设置的控制栅极和浮置栅极，以及 仅在读取期间将电压施加到源极和漏极，以便读取数据。

公开(公告)号：US08012835B2

公开(公告)日：2011-09-06

申请号：US12283639

申请日：2008-09-12

申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

IPC分类号： H01L21/8234

CPC分类号： H01L27/0629 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/78645 ,  H01L29/78654

摘要： A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.

摘要翻译： 高电压工作场效应晶体管具有在衬底的表面中彼此间隔开的源极区和漏极区。 源区域可操作以接收信号电位和信号电流中的至少一个。 半导体沟道形成区域设置在源极区域和漏极区域之间的衬底的表面中。 栅极区域设置在沟道形成区域上方，并且可操作以接收具有等于或大于根据漏极电位的增加或减小而改变的第一恒定电位的绝对值的偏置电位。 栅极绝缘膜区域设置在沟道形成区域和栅极区域之间。

公开(公告)号：US07816212B2

公开(公告)日：2010-10-19

申请号：US12283638

申请日：2008-09-12

申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

IPC分类号： H01L21/8234

CPC分类号： H01L29/4238

摘要： A high voltage operating field effect transistor has a substrate and a semiconductor channel formation region disposed in a surface of the substrate. A source region and a drain region are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region. A gate insulating film region is disposed on the semiconductor channel formation region. A resistive gate region is disposed on the gate insulating film region. A source side electrode is disposed on a source region side of the resistive gate region and is operative to receive a signal electric potential. A drain side electrode is disposed on a drain region side of the resistive gate region and is operative to receive a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential.

摘要翻译： 高电压工作场效应晶体管具有衬底和设置在衬底的表面中的半导体沟道形成区域。 源极区域和漏极区域彼此间隔开，半导体沟道形成区域设置在源极区域和漏极区域之间。 栅极绝缘膜区域设置在半导体沟道形成区域上。 电阻栅极区域设置在栅极绝缘膜区域上。 源极电极设置在电阻栅极区域的源极区域侧并且可操作以接收信号电位。 漏极侧电极设置在电阻栅极区域的漏极侧，并且可操作以接收其绝对值等于或大于指定电位的绝对值的偏置电位，并且其根据增加或 降低漏极电位。

公开(公告)号：US07749880B2

公开(公告)日：2010-07-06

申请号：US11196095

申请日：2005-08-03

申请人： Jun Osanai

发明人： Jun Osanai

IPC分类号： H01L21/336 ,  H01L27/088

CPC分类号： H01L21/823468 ,  H01L21/3003 ,  H01L21/823412 ,  H01L27/0207

摘要： In a method of manufacturing a semiconductor integrated circuit device, a gate electrode is formed over a semiconductor substrate. An insulating film is then formed on the gate electrode and on regions corresponding to a source and a drain of the semiconductor integrated circuit device. The source and the drain are then formed. A nitride film is then selectively formed over the source and the gate electrode via the insulating film so that the nitride film extends over the gate electrode to a position short of a center of the gate electrode in a length direction thereof and so that a width of the nitride film is shorter than a channel width of the semiconductor integrated circuit device.

摘要翻译： 在制造半导体集成电路器件的方法中，在半导体衬底上形成栅电极。 然后在栅电极和对应于半导体集成电路器件的源极和漏极的区域上形成绝缘膜。 然后形成源极和漏极。 然后通过绝缘膜在源极和栅电极上选择性地形成氮化物膜，使得氮化物膜在栅电极上延伸到栅极电极的长度方向上的中心不到的位置， 氮化物膜比半导体集成电路器件的沟道宽度短。