公开(公告)号：US07494883B2

公开(公告)日：2009-02-24

申请号：US11543213

申请日：2006-10-05

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60〜120keV，通道阻挡层的密度为1×10 17〜1×10 19 / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。

公开(公告)号：US07067881B2

公开(公告)日：2006-06-27

申请号：US10754539

申请日：2004-01-12

申请人： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

发明人： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

IPC分类号： H01L27/01

CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7845

摘要： A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

摘要翻译： 提供一种半导体器件及其制造方法，其可以适当地避免隔离击穿电压的降低，而不会引起诸如结电容增加的不利影响。 在通过形成凹部（14）使硅层（3）变薄之后形成杂质导入区域（11）。 因此，在位于元件隔离绝缘膜（5）的底部和BOX层（2）的顶面之间的p型硅层（3）的部分中不会注入n型杂质，避免了还原 的隔离击穿电压。 此外，由于杂质引入区域（11）形成为到达BOX层（2）的上表面，所以源极/漏极区域（12）的结电容不增加。

公开(公告)号：US20050156242A1

公开(公告)日：2005-07-21

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

公开(公告)号：US20050101091A1

公开(公告)日：2005-05-12

申请号：US11011655

申请日：2004-12-15

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786 ,  H01L21/8242 ,  H01L21/8234

CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60至120keV，并且通道阻挡层的密度设定为1×10 17至1×10 19 / SUP> / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。

公开(公告)号：US06875663B2

公开(公告)日：2005-04-05

申请号：US10237022

申请日：2002-09-09

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60至120keV，并且通道阻挡层的密度设定为1×10 17至1×10 19 / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。

公开(公告)号：US06794717B2

公开(公告)日：2004-09-21

申请号：US09986004

申请日：2001-11-07

申请人： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2701

CPC分类号： H01L29/78615 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S257/904

摘要： It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “-” functions as a gate electrode of an original MOS transistor.

摘要翻译： 本发明的目的是提供具有SOI结构的半导体器件，其中可以以高稳定性固定由部分隔离区隔离的元件形成区域中的体区的电位。 在由部分氧化膜（31）隔离的元件形成区域中形成包括源极区（51），漏极区（61）和H栅电极（71）的MOS晶体管。 H栅电极（71）将从栅极宽度W方向形成的主体区域（13）与漏极区域（61）和源极区域（51）的源极区域（51）和漏极区域（61）相邻地隔离 ）通过“I”横向（图中的垂直方向），中心“ - ”用作原始MOS晶体管的栅电极。

公开(公告)号：US06627512B2

公开(公告)日：2003-09-30

申请号：US10090607

申请日：2002-03-06

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

IPC分类号： H01L2176

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L27/1203

摘要： In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

公开(公告)号：US06495898B1

公开(公告)日：2002-12-17

申请号：US09639953

申请日：2000-08-17

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

IPC分类号： H01L2900

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L27/1203

摘要： In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

摘要翻译： 在组合隔离氧化膜（BT1）中，靠近栅电极（GT13）的部分通过SOI层（3）到达埋入氧化膜（2），而靠近另一栅电极（GT12）的部分具有截面形状 在其下部设置有井区。 组合隔离氧化膜（BT1）的边缘部分的形状在LOCOS隔离氧化膜中呈鸟喙的形式。 因此，限定栅极氧化膜（GO12，GO13）的边缘部分的部分的厚度局部增加。 这样提供了一种半导体器件及其制造方法，该半导体器件包括具有防止绝缘击穿而不增加其厚度的栅极氧化膜的MOS晶体管。

公开(公告)号：US06953979B1

公开(公告)日：2005-10-11

申请号：US09466934

申请日：1999-12-20

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US06646306B2

公开(公告)日：2003-11-11

申请号：US09985020

申请日：2001-11-01

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

IPC分类号： H01L2701

CPC分类号： H01L21/76286 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458

摘要： A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.

摘要翻译： 一种防止金属污染的半导体器件以及半导体器件的制造方法。 区域（NR）和区域（PR）由沟槽隔离氧化膜，选择性地设置在沟槽隔离氧化膜上的多晶硅膜，设置在多晶硅膜上的硅层和设置在侧面上的侧壁隔离物 多晶硅膜的表面。 多晶硅膜设置在对应于跨越两个阱区域的SOI层中的P型阱区域和N型阱区域的PN结部分JP的顶部的位置。