公开(公告)号：US09252793B2

公开(公告)日：2016-02-02

申请号：US13990030

申请日：2010-11-29

申请人： Toshiaki Tsutsumi ,  Yoshihiro Funato ,  Tomonori Okudaira ,  Tadato Yamagata ,  Akihisa Uchida ,  Takeshi Terasaki ,  Tomohisa Suzuki ,  Yoshiharu Kanegae

发明人： Toshiaki Tsutsumi ,  Yoshihiro Funato ,  Tomonori Okudaira ,  Tadato Yamagata ,  Akihisa Uchida ,  Takeshi Terasaki ,  Tomohisa Suzuki ,  Yoshiharu Kanegae

IPC分类号： H03L7/24 ,  H01L23/522 ,  H01L27/06 ,  H01L23/31 ,  H01L23/00

CPC分类号： H03B5/24 ,  H01L23/3107 ,  H01L23/5228 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554 ,  H01L2224/06179 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01015 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H03L7/24 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage. The reference resistor is formed of a plurality of resistors, which extend in a first (Y) direction orthogonal to a first side, inside a first region (RG1, RG2, RG3, and RG4) surrounded by the first side (S1, S2, S3, and S4) of a main surface of the semiconductor chip (CP1), a first line (42, 43, 44, and 45) connecting between one end of the first side and the center (CT1) of the main surface of the semiconductor chip, and a second line (42, 43, 44, and 45) connecting between the other end of the first side and the center of the main surface of the semiconductor chip.

公开(公告)号：US20130314165A1

公开(公告)日：2013-11-28

申请号：US13990030

申请日：2010-11-29

申请人： Toshiaki Tsutsumi ,  Yoshihiro Funato ,  Tomonori Okudaira ,  Tadato Yamagata ,  Akihisa Uchida ,  Takeshi Terasaki ,  Tomohisa Suzuki ,  Yoshiharu Kanegae

发明人： Toshiaki Tsutsumi ,  Yoshihiro Funato ,  Tomonori Okudaira ,  Tadato Yamagata ,  Akihisa Uchida ,  Takeshi Terasaki ,  Tomohisa Suzuki ,  Yoshiharu Kanegae

IPC分类号： H03L7/24

CPC分类号： H03B5/24 ,  H01L23/3107 ,  H01L23/5228 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554 ,  H01L2224/06179 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01015 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H03L7/24 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage. The reference resistor is formed of a plurality of resistors, which extend in a first (Y) direction orthogonal to a first side, inside a first region (RG1, RG2, RG3, and RG4) surrounded by the first side (S1, S2, S3, and S4) of a main surface of the semiconductor chip (CP1), a first line (42, 43, 44, and 45) connecting between one end of the first side and the center (CT1) of the main surface of the semiconductor chip, and a second line (42, 43, 44, and 45) connecting between the other end of the first side and the center of the main surface of the semiconductor chip.

摘要翻译： 通过用树脂密封具有利用参考电阻器的振荡电路的半导体芯片（CP1）形成半导体器件。 振荡电路利用参考电阻产生参考电流，根据该参考电流产生电压和振荡单元的振荡频率，并且振荡单元根据所产生的电压以频率振荡。 参考电阻器由多个电阻器构成，该多个电阻器在与第一侧面正交的第一（Y）方向上在由第一侧（S1，S2，RG3，RG3和RG4）包围的第一区域（RG1，RG2， S3和S4），连接在第一侧的一端与第一侧的主表面的中心（CT1）之间的第一线（42,43,44和45） 半导体芯片和连接在第一侧的另一端和半导体芯片的主表面的中心之间的第二线（42,43,44和45）。

公开(公告)号：US08148248B2

公开(公告)日：2012-04-03

申请号：US13053733

申请日：2011-03-22

申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

公开(公告)号：US20070077736A1

公开(公告)日：2007-04-05

申请号：US11537208

申请日：2006-09-29

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L21/04

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US20110207317A1

公开(公告)日：2011-08-25

申请号：US13053733

申请日：2011-03-22

申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

IPC分类号： H01L21/768

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

公开(公告)号：US07872314B2

公开(公告)日：2011-01-18

申请号：US12727334

申请日：2010-03-19

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L23/62

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US07696050B2

公开(公告)日：2010-04-13

申请号：US11537208

申请日：2006-09-29

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US20100171183A1

公开(公告)日：2010-07-08

申请号：US12727334

申请日：2010-03-19

申请人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US20080121950A1

公开(公告)日：2008-05-29

申请号：US11771340

申请日：2007-06-29

申请人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7848

摘要： Even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is realized.The channel length direction of n channel MISFET where the silicide region of nickel or a nickel alloy was formed on the source and the drain is arranged so that it may become parallel to the crystal orientation of a semiconductor substrate. Since it is hard to extend the silicide region of nickel or a nickel alloy in the direction of crystal orientation , even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is obtained.

摘要翻译： 即使是在n沟道MISFET的源极和漏极中形成镍或镍合金的硅化物区域的情况，也可以实现OFF泄漏电流容易增加的半导体器件。 在源极和漏极上形成镍或镍合金的硅化物区域的n沟道MISFET的沟道长度方向被布置成使其可以平行于半导体衬底的晶体取向<100>。 由于难以在晶体取向<100>的方向上延伸镍或镍合金的硅化物区域，所以即使在镍或镍合金的硅化物区域形成在n的源极和漏极中的情况 通道MISFET，可以容易地提高OFF漏电流的半导体装置。

公开(公告)号：US08338247B2

公开(公告)日：2012-12-25

申请号：US12720174

申请日：2010-03-09

申请人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

发明人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

摘要翻译： 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。