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    Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove
    3.
    发明授权
    Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove 失效
    在公共衬底上形成的半导体集成电路器件通过由沟槽隔离的场氧化物和双极晶体管隔离的MISFET

    公开(公告)号：US5214302A

    公开(公告)日：1993-05-25

    申请号：US807411

    申请日：1991-12-13

    申请人： Akihisa Uchida ,  Keiichi Higeta ,  Nobuo Tamba ,  Masanori Odaka ,  Katsumi Ogiue

    发明人： Akihisa Uchida ,  Keiichi Higeta ,  Nobuo Tamba ,  Masanori Odaka ,  Katsumi Ogiue

    IPC分类号： H01L27/06 ,  H01L27/11 ,  H01L29/732

    CPC分类号： H01L29/7325 ,  H01L27/0623 ,  H01L27/1112

    摘要： A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region. The bipolar transistor is characterized as a self-alignment transistor and that the insulating side wall spacers corresponding to the gate and base (emitter) electrodes are formed by a same lever.

    摘要翻译： 一种半导体集成电路器件，具有以下结构，其中以下各个区域，即用于形成每个双极晶体管的基极和发射极区域的第一区域，用于形成双极性的集电极导出区域的第二区域 晶体管和用于形成每个MISFET的第三区域从半导体衬底的主表面突出，由此可以实现MISFET之间以及这些MISFET与具有相同隔离结构的双极晶体管之间的隔离，并且在 与双极晶体管之间的隔离相同的制造步骤。 此外，在该器件中，双极晶体管的基极区域电自自对准地连接到形成在主表面上以围绕发射极区域的基极。 双极晶体管的特征在于自对准晶体管，并且与栅极和基极（发射极）电极对应的绝缘侧壁间隔物由相同的杆形成。

    Bipolar static RAM having two wiring lines for each word line
    8.
    发明授权
    Bipolar static RAM having two wiring lines for each word line 失效
    双极静态RAM，每条字线具有两条接线

    公开(公告)号：US4926378A

    公开(公告)日：1990-05-15

    申请号：US160259

    申请日：1988-02-25

    申请人： Akihisa Uchida ,  Ichiro Mitamura ,  Keiichi Higeta

    发明人： Akihisa Uchida ,  Ichiro Mitamura ,  Keiichi Higeta

    IPC分类号： H01L29/73 ,  G11C11/415 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8229 ,  H01L23/52 ,  H01L27/06 ,  H01L27/10 ,  H01L27/102 ,  H01L29/732

    CPC分类号： G11C11/415

    摘要： There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a common signal therethrough such as with respect to the individual word lines. The word lines implemented are formed from at least a pair of stacked conductive layers of a material whose principal component is aluminum and which layers have interposed therebetween an insulating film. The pair of layers form a pair of wiring lines corresponding together to a word line and wherein the wiring lines are, furthermore, interconnected at predetermined intervals along the lengths thereof. This leads to the ability to decrease the chip size of semiconductor integrated circuits noting that a decrease in the voltage drop of a signal line results, and to prevent electromigration in the signal (wiring) lines.

    摘要翻译： 在双极型静态随机存取存储器中实现存储单元和与之相关联的相应的信号线，该双极型静态随机存取存储器采用多层结构的布线，用于通过其传送公共信号，例如相对于各个字线。 所实施的字线由主要成分为铝的材料的至少一对叠层导电层形成，并且其间插入有绝缘膜。 这对层形成一对与字线对应的布线，并且其中布线还沿着其长度以预定间隔互连。 这导致降低半导体集成电路的芯片尺寸的能力，注意到信号线的电压降降低，并且防止信号（布线）线路中的电迁移。

    Method of manufacturing a semiconductor device
    10.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07073147B2

    公开(公告)日：2006-07-04

    申请号：US10694825

    申请日：2003-10-29

    申请人： Hiroyuki Ikeda ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

    发明人： Hiroyuki Ikeda ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

    IPC分类号： G06F17/50

    CPC分类号： H01L27/11 ,  G11C5/14 ,  H01L27/0207

    摘要： Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.

    摘要翻译： 连接到用于衬底偏置电路的从属开关电路单元的栅电极的布线分别电连接到用于电源电位的布线和用于参考电位的布线。 因此，从开关电路单元的开关动作无效。 连接到各个电路单元的n个阱的布线电连接到用于电源电位的布线，并且连接到各个电路单元的p阱的布线电连接到布线。 因此，n个阱被固定到电源电位，并且p阱被固定到参考电位。