利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

44 条记录 (耗时 0.023 秒)

    METHOD OF CORRECTING MASK PATTERN, COMPUTER PROGRAM PRODUCT, MASK PATTERN CORRECTING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD OF CORRECTING MASK PATTERN, COMPUTER PROGRAM PRODUCT, MASK PATTERN CORRECTING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    校正掩模图案，计算机程序产品，掩模图案校正装置的方法和制造半导体器件的方法

    公开(公告)号：US20120244707A1

    公开(公告)日：2012-09-27

    申请号：US13239019

    申请日：2011-09-21

    申请人： Taiga Uno ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Yukiyasu Arisawa

    发明人： Taiga Uno ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Yukiyasu Arisawa

    IPC分类号： G03F1/70 ,  H01L21/311 ,  G06F17/50

    CPC分类号： G03F1/36 ,  G03F1/70 ,  G03F7/70441 ,  G03F7/70941

    摘要： In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value.

    摘要翻译： 在根据实施例的校正掩模图案的方法中，对于布局中的每种类型的图案，计算用于参考闪光值的掩模图案校正量作为参考掩模校正量，以及掩模图案校正的改变量 计算与闪光值的变化量对应的量作为变化量信息。 基于从具有图案的信息提取参考掩模校正量和变化量信息相关联的参考掩模校正量和对应于图案的改变量信息，创建与图案的闪光值相对应的掩模图案 并且基于图案的耀斑值和参考闪光值之间的差异。

    Method of correcting mask pattern, computer program product, and method of manufacturing semiconductor device
    2.
    发明授权
    Method of correcting mask pattern, computer program product, and method of manufacturing semiconductor device 有权
    掩模图案校正方法，计算机程序产品和半导体器件制造方法

    公开(公告)号：US08617773B2

    公开(公告)日：2013-12-31

    申请号：US13239019

    申请日：2011-09-21

    申请人： Taiga Uno ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Yukiyasu Arisawa

    发明人： Taiga Uno ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Yukiyasu Arisawa

    IPC分类号： G03F1/44 ,  G03F1/72 ,  G03F1/38

    CPC分类号： G03F1/36 ,  G03F1/70 ,  G03F7/70441 ,  G03F7/70941

    摘要： In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value.

    摘要翻译： 在根据实施例的校正掩模图案的方法中，对于布局中的每种类型的图案，计算用于参考闪光值的掩模图案校正量作为参考掩模校正量，以及掩模图案校正的改变量 计算与闪光值的变化量对应的量作为变化量信息。 基于从具有图案的信息提取参考掩模校正量和变化量信息相关联的参考掩模校正量和对应于图案的改变量信息，创建与图案的闪光值相对应的掩模图案 并且基于图案的耀斑值和参考闪光值之间的差异。

    PATTERN DETERMINING METHOD
    3.
    发明申请
    PATTERN DETERMINING METHOD 审中-公开
    图案确定方法

    公开(公告)号：US20110047518A1

    公开(公告)日：2011-02-24

    申请号：US12860278

    申请日：2010-08-20

    申请人： Issui Aiba ,  Takafumi Taguchi ,  Hiromitsu Mashita ,  Taiga Uno ,  Fumiharu Nakajima ,  Toshiya Kotani ,  Tadahito Fujisawa

    发明人： Issui Aiba ,  Takafumi Taguchi ,  Hiromitsu Mashita ,  Taiga Uno ,  Fumiharu Nakajima ,  Toshiya Kotani ,  Tadahito Fujisawa

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36

    摘要： According to the embodiments, a first representative point is set on outline pattern data on a pattern formed in a process before a processed pattern. Then, a minimum distance from the first representative point to a peripheral pattern is calculated. Then, area of a region with no pattern, which is sandwiched by the first representative point and the peripheral pattern, in a region within a predetermined range from the first representative point is calculated. Then, it is determined whether the first representative point becomes a processing failure by using the minimum distance and the area.

    摘要翻译： 根据实施例，在处理图案之前的处理中形成的图案上的轮廓图案数据上设置第一代表点。 然后，计算从第一代表点到外围图案的最小距离。 然后，计算出与第一代表点和外围图案夹着的没有图案的区域的区域在距离第一代表点的预定范围内的区域中。 然后，通过使用最小距离和面积确定第一代表点是否变为处理失败。

    Method of fabricating semiconductor device and semiconductor device
    7.
    发明授权
    Method of fabricating semiconductor device and semiconductor device 有权
    制造半导体器件和半导体器件的方法

    公开(公告)号：US08183148B2

    公开(公告)日：2012-05-22

    申请号：US12542540

    申请日：2009-08-17

    申请人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

    发明人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

    摘要翻译： 根据实施例的制造半导体器件的方法包括在基底层上形成具有恒定线宽度和第二图案的线性部分的第一图案，第二图案包括靠近第一图案的线性部分的部分和部分离开 从第一图案的直线部分和独立于第一图案构成闭环形状，或者处于连接到第一图案的状态，并且在第二图案的部分处远离线形部分进行闭环切割 第一种模式

    Mask pattern data generation method, mask manufacturing method, semiconductor device manufacturing method, and pattern data generation program
    8.
    发明授权
    Mask pattern data generation method, mask manufacturing method, semiconductor device manufacturing method, and pattern data generation program 有权
    掩模图案数据生成方法，掩模制造方法，半导体器件制造方法和图案数据生成程序

    公开(公告)号：US08146022B2

    公开(公告)日：2012-03-27

    申请号：US12409068

    申请日：2009-03-23

    申请人： Hiromitsu Mashita ,  Toshiya Kotani ,  Takashi Obara

    发明人： Hiromitsu Mashita ,  Toshiya Kotani ,  Takashi Obara

    IPC分类号： G06F17/50 ,  G06K9/00

    CPC分类号： G03F1/36

    摘要： According to an aspect of the present invention, there is provided a mask pattern data generation method including: a first step of obtaining a mask data representing from a design pattern by performing a process simulation with a process parameter having a first value; a second step of obtaining a finished pattern from the mask data by performing the process simulation with the process parameter having a different value; a third step of verifying whether a dimensional error therebetween is within an allowable range; and a fourth step of: if the dimensional error is within the allowable range, determining the mask pattern data; and if the dimensional error is not within the allowable range, repeating the above steps by updating the process parameter until the dimensional error becomes within the allowable range.

    摘要翻译： 根据本发明的一个方面，提供了一种掩模图案数据生成方法，包括：第一步骤，通过利用具有第一值的处理参数进行处理模拟来获得表示设计图案的掩模数据; 通过使用具有不同值的处理参数进行处理模拟从掩模数据获得完成图案的第二步骤; 验证其间的尺寸误差是否在允许范围内的第三步骤; 以及第四步骤：如果所述尺寸误差在所述容许范围内，则确定所述掩模图案数据; 并且如果尺寸误差不在允许范围内，则通过更新处理参数重复上述步骤，直到尺寸误差变得在允许范围内。

    Pattern verification method, method of manufacturing semiconductor device, and recording media
    9.
    发明授权
    Pattern verification method, method of manufacturing semiconductor device, and recording media 失效
    模式验证方法，制造半导体器件的方法和记录介质

    公开(公告)号：US08108824B2

    公开(公告)日：2012-01-31

    申请号：US12420931

    申请日：2009-04-09

    申请人： Toshiya Kotani ,  Hiromitsu Mashita ,  Kazuhito Kobayashi

    发明人： Toshiya Kotani ,  Hiromitsu Mashita ,  Kazuhito Kobayashi

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36 ,  G03F1/68

    摘要： A pattern verification method according to an embodiment includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions, calculating a pattern area ratio with respect to each unit region, calculating differences in the amount of the pattern area ratio between each unit region and adjacent unit regions thereto, setting the number or density of measurement point with respect to each unit region to the pattern of the pattern data region or the pattern formation region according to the difference in the amount of pattern area ratio, measuring the pattern size at each measurement point, and verifying whether the size measurement value is within a predetermined range or not.

    摘要翻译： 根据实施例的图案验证方法包括：将基于图案数据形成的图案数据区域或图案形成区域划分为多个单位区域，计算相对于每个单位区域的图案面积比，计算量的差异 每个单位区域与相邻单位区域之间的图案面积比率，将测量点的数量或密度相对于每个单位区域设置为图案数据区域或图案形成区域的图案，根据 测量每个测量点处的图案尺寸，以及验证尺寸测量值是否在预定范围内。

    Method for manufacturing semiconductor device
    10.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07713833B2

    公开(公告)日：2010-05-11

    申请号：US12557111

    申请日：2009-09-10

    申请人： Hiromitsu Mashita ,  Toshiya Kotani ,  Hidefumi Mukai ,  Fumiharu Nakajima ,  Chikaaki Kodama

    发明人： Hiromitsu Mashita ,  Toshiya Kotani ,  Hidefumi Mukai ,  Fumiharu Nakajima ,  Chikaaki Kodama

    IPC分类号： H01L21/76

    CPC分类号： H01L27/11524 ,  H01L21/0337 ,  H01L21/32139

    摘要： According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.

    摘要翻译： 根据本发明的一个方面，提供一种制造半导体器件的方法，所述方法包括：在靶膜上形成第一膜; 在第一膜上形成抗蚀剂图案; 用抗蚀剂图案处理第一膜以形成第一图案，包括：周期图案; 和非周期性模式; 去除抗蚀剂图案; 在目标膜上形成第二膜; 处理所述第二膜以在所述第一图案的侧壁上形成第二侧壁图案; 去除周期性模式; 用非周期图案和第二侧壁图案处理目标薄膜，从而形成包括周期性目标图案的目标图案; 非周期目标模式; 以及布置在周期性目标图案和非周期性图案之间的虚拟图案，并且周期性地布置有周期性目标图案。