公开(公告)号：US20080238453A1

公开(公告)日：2008-10-02

申请号：US11731444

申请日：2007-03-30

申请人： Tseng Chin Lo ,  Kuo-Tsai Li ,  Shien-Yang Wu

发明人： Tseng Chin Lo ,  Kuo-Tsai Li ,  Shien-Yang Wu

IPC分类号： G01R31/02

CPC分类号： G01R31/2884 ,  G01R31/2831 ,  G01R31/2891 ,  H01L2924/0002 ,  H01L2924/00

摘要： A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.

摘要翻译： 介绍了用于集成电路测试的测试线结构。 该结构包括形成在半导体衬底上的划线区域或集成电路管芯区域中的测试线焊盘阵列，形成在焊盘区域下方的多个测试设备以及选择性地连接其中一个测试设备的选择电路。 本发明的测试线结构能够通过与常规测试线上相同数量的焊盘来访问大量的测试设备，并且可以用它来进行参数，可靠性和功能测试。 采用常规集成电路测试仪中的源测量单元（SMU）来感测和强制测试设备端子上的预定测试条件，并在所选设备上进行准确的开尔文测试。 还提出了使用该测试线结构的方法。

公开(公告)号：US20080244475A1

公开(公告)日：2008-10-02

申请号：US11731036

申请日：2007-03-30

申请人： Tseng Chin Lo ,  Kuo Tsai Li ,  Shien-Yang Wu

发明人： Tseng Chin Lo ,  Kuo Tsai Li ,  Shien-Yang Wu

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/14

摘要： A network based integrated circuit testline generating system and method of using the same is described. The system includes a user interface for generating and submitting requests which specify types and configurations of needed testlines for device parametric test. A testline generator receives the requests and creates a layout data base which includes layout information of needed testlines.

摘要翻译： 描述了基于网络的集成电路测试线生成系统及其使用方法。 该系统包括用于生成和提交请求的用户界面，该请求指定用于设备参数测试的所需测试线的类型和配置。 测试线生成器接收请求并创建一个布局数据库，其中包含所需测试线的布局信息。

公开(公告)号：US07782073B2

公开(公告)日：2010-08-24

申请号：US11731444

申请日：2007-03-30

申请人： Tseng Chin Lo ,  Kuo-Tsai Li ,  Shien-Yang Wu

发明人： Tseng Chin Lo ,  Kuo-Tsai Li ,  Shien-Yang Wu

IPC分类号： G01R31/26

CPC分类号： G01R31/2884 ,  G01R31/2831 ,  G01R31/2891 ,  H01L2924/0002 ,  H01L2924/00

摘要： A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.

摘要翻译： 介绍了用于集成电路测试的测试线结构。 该结构包括形成在半导体衬底上的划线区域或集成电路管芯区域中的测试线焊盘阵列，形成在焊盘区域下方的多个测试设备以及选择性地连接其中一个测试设备的选择电路。 本发明的测试线结构能够通过与常规测试线上相同数量的焊盘来访问大量的测试设备，并且可以用它来进行参数，可靠性和功能测试。 采用常规集成电路测试仪中的源测量单元（SMU）来感测和强制测试设备端子上的预定测试条件，并在所选设备上进行准确的开尔文测试。 还提出了使用该测试线结构的方法。

公开(公告)号：US06323097B1

公开(公告)日：2001-11-27

申请号：US09590183

申请日：2000-06-09

申请人： Shien-Yang Wu ,  Tseng Chin Lo ,  Konrad Young

发明人： Shien-Yang Wu ,  Tseng Chin Lo ,  Konrad Young

IPC分类号： H01L2120

CPC分类号： H01L22/32 ,  G01B7/003 ,  H01L22/34

摘要： A method and structure is disclosed to measure spacing and misalignment of features in semiconductor integrated circuits. Three equally spaced, parallel first level conductive lines are formed on a first insulating layer with staircase patterns projecting both out of and into the inner edges of the outer lines. A second insulating layer is deposited and step contact vias are opened through the second insulating layer over the steps of the staircase patterns. The inner edge of the step contact via coincides with the inner edge of the step. Contact pad vias are opened through the second insulating layer over the outer lines and the step contact vias and the contact pad vias are filled with conductive material. A second level conductive line is formed over the second insulating layer parallel to said first level conductive lines and above the central first level conductive line. Resistor ladder patterns are formed projecting from both edges of said second level conductive line, the rungs of said ladder patterns being of equal length and being composed of rung conductive sections with a resistor section interposed. A center conductor contact pad is formed electrically connected to the second level conductive line. A right conductor contact pad is formed over the right contact pad via and a left conductor contact pad is formed over the left contact pad via. The resistances between the center conductor pad and the right conductor pad and between the center conductor pad and left conductor pad are measured. From these resistances are inferred which rungs of the resistor ladder patterns make contact with step contact vias of the outer first level conductive lines. This infers bounds for the distances, SR and SL, from the right and left outer first level conductive lines to the second level conductive line. Spacing and misalignment are calculated from these distances.

摘要翻译： 公开了一种用于测量半导体集成电路中的特征的间隔和未对准的方法和结构。 在第一绝缘层上形成三个等间隔的平行的第一级导电线，该第一绝缘层具有从外线的内边缘突出并进入外线的内边缘的阶梯图案。 沉积第二绝缘层，并且在台阶图案的台阶上通过第二绝缘层打开阶梯接触通孔。 台阶接触孔的内边缘与台阶的内边缘重合。 接触焊盘通孔在外线上通过第二绝缘层打开，并且步骤接触通孔和接触焊盘通孔填充有导电材料。 第二级导电线形成在平行于所述第一级导电线并且在中心第一级导电线上方的第二绝缘层上。 电阻梯形图案从所述第二电平导线的两个边缘突出形成，所述梯形图案的梯级具有相等的长度，并且由插入有电阻器部分的梯形导电部分组成。 形成电连接到第二电平导线的中心导体接触焊盘。 在右接触焊盘上形成右导体接触焊盘，并且在左接触焊盘通孔上形成左导体接触焊盘。 测量中心导体焊盘和右导体焊盘之间以及中心导体焊盘和左导体焊盘之间的电阻。 从这些电阻推断出电阻梯形图案的哪个梯级与外部第一级导电线的阶跃接触通孔接触。 这推断了从左右外一级导线到第二级导线的距离SR和SL。 从这些距离计算间距和不对中。

公开(公告)号：US08629050B2

公开(公告)日：2014-01-14

申请号：US13443550

申请日：2012-04-10

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry-Hak-Lay Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry-Hak-Lay Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L21/02

CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US20070290277A1

公开(公告)日：2007-12-20

申请号：US11844161

申请日：2007-08-23

申请人： Sun-Jay Chang ,  Shien-Yang Wu

发明人： Sun-Jay Chang ,  Shien-Yang Wu

IPC分类号： H01L29/94

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7849

摘要： A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.

摘要翻译： 提供一种用于制造具有由硅 - 锗组分构成的沟道区的MOSFET器件的工艺。 工艺特征采用成角度的离子注入方法，将锗离子放置在导电栅极结构下面的半导体衬底的区域中。 用作随后的高掺杂源极/漏极区域的扩散源的凸起硅形状的存在，导电栅极结构的存在以及先前位于导电栅极结构上的虚设绝缘体的去除允许成角度的注入过程放置 在半导体衬底的用于MOSFET沟道区域的部分中的锗离子。 退火程序导致在用于MOSFET沟道区的半导体衬底的部分中形成所需的硅 - 锗组分。

公开(公告)号：US07279430B2

公开(公告)日：2007-10-09

申请号：US10919684

申请日：2004-08-17

申请人： Sun-Jay Chang ,  Shien-Yang Wu

发明人： Sun-Jay Chang ,  Shien-Yang Wu

IPC分类号： H01L21/302

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7849

摘要： A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.

摘要翻译： 提供一种用于制造具有由硅 - 锗组分构成的沟道区的MOSFET器件的工艺。 工艺特征采用成角度的离子注入方法，将锗离子放置在导电栅极结构下面的半导体衬底的区域中。 用作随后的重掺杂源极/漏极区域的扩散源的凸起硅形状的存在，导电栅极结构的存在以及先前位于导电栅极结构上的虚设绝缘体的去除允许成角度的注入过程将锗 半导体衬底的一部分中用于MOSFET沟道区的离子。 退火程序导致在用于MOSFET沟道区的半导体衬底的部分中形成所需的硅 - 锗组分。

公开(公告)号：US20050277232A1

公开(公告)日：2005-12-15

申请号：US11207634

申请日：2005-08-19

申请人： Shien-Yang Wu ,  Shi-Bai Chen

发明人： Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L21/768 ,  H01L21/82 ,  H01L23/525 ,  H01L29/00 ,  H01L29/36 ,  H01L29/74 ,  H01L29/861

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： System and method for providing an electrical fuse having a p-n junction diode. A preferred embodiment comprises a cathode, an anode, and one or more links formed between the cathode and the anode. The cathode and the portion of the cathode adjoining the link are doped with a first impurity, preferably a p-type impurity. The anode and the portion of the link adjoining the anode are doped with a second impurity, preferably an n-type impurity. The junction of the first impurity and the second impurity in the link forms a p-n junction diode. A conductive layer, such as a silicide layer, is formed over the p-n junction diodes. In an alternative embodiment, a plurality of p-n junction diodes may be formed in each link. One or more contacts may be formed to provide electrical contact to the cathode and the anode.

公开(公告)号：US06956277B1

公开(公告)日：2005-10-18

申请号：US10806955

申请日：2004-03-23

申请人： Shien-Yang Wu ,  Shi-Bai Chen

发明人： Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L21/768 ,  H01L21/82 ,  H01L23/525 ,  H01L29/00 ,  H01L29/36 ,  H01L29/74 ,  H01L29/861

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： System and method for providing an electrical fuse having a p-n junction diode. A preferred embodiment comprises a cathode, an anode, and one or more links formed between the cathode and the anode. The cathode and the portion of the cathode adjoining the link are doped with a first impurity, preferably a p-type impurity. The anode and the portion of the link adjoining the anode are doped with a second impurity, preferably an n-type impurity. The junction of the first impurity and the second impurity in the link forms a p-n junction diode. A conductive layer, such as a silicide layer, is formed over the p-n junction diodes. In an alternative embodiment, a plurality of p-n junction diodes may be formed in each link. One or more contacts may be formed to provide electrical contact to the cathode and the anode.

摘要翻译： 用于提供具有p-n结二极管的电熔丝的系统和方法。 优选实施例包括阴极，阳极和形成在阴极和阳极之间的一个或多个连接。 邻接连接的阴极和阴极部分掺杂有第一杂质，优选p型杂质。 阳极和邻接阳极的连接部分掺杂有第二杂质，优选为n型杂质。 连接中的第一杂质和第二杂质的结形成p-n结二极管。 在p-n结二极管上形成诸如硅化物层的导电层。 在替代实施例中，可以在每个链路中形成多个p-n结二极管。 可以形成一个或多个触点以提供与阴极和阳极的电接触。

公开(公告)号：US06580145B2

公开(公告)日：2003-06-17

申请号：US09761294

申请日：2001-01-16

申请人： Shien-Yang Wu ,  Ta-Lee Yu

发明人： Shien-Yang Wu ,  Ta-Lee Yu

IPC分类号： H01L2900

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： Within both an anti-fuse structure and a method for operating the anti-fuse structure there is employed a semiconductor substrate having a first region adjoining a second region, where there is formed a metal oxide semiconductor field effect transistor within and upon the first region of the semiconductor substrate and a metal oxide semiconductor capacitor within the upon the second region of the semiconductor substrate. Further, within the anti-fuse structure: (1) a gate dielectric layer within the metal oxide semiconductor field effect transistor is thicker than a capacitive dielectric layer within the metal oxide semiconductor capacitor; and (2) the metal oxide semiconductor capacitor is formed employing as a first capacitor plate a doped well within the semiconductor substrate of equivalent polarity with and overlapping with a source/drain region within the metal oxide semiconductor field effect transistor. The anti-fuse structure has a comparatively low programming voltage which does not electrically overstress adjacent microelectronic devices.