公开(公告)号：US06384674B2

公开(公告)日：2002-05-07

申请号：US09353349

申请日：1999-07-15

申请人： Hiroaki Tanizaki ,  Tsukasa Ooishi ,  Shigeki Tomishima ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Takaharu Tsuji

发明人： Hiroaki Tanizaki ,  Tsukasa Ooishi ,  Shigeki Tomishima ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Takaharu Tsuji

IPC分类号： G05F110

CPC分类号： G11C5/063 ,  G11C11/4074 ,  G11C11/4097 ,  H02J1/06

摘要： Provided is a power supply-to-power supply capacitance cell including a first capacitor connected between a sub power supply line and a sub ground line, a second capacitor connected between a main power supply line and the sub ground line, and a third capacitor connected between the sub power supply line and a main ground line. Thus, a voltage drop of the sub power supply line can be reduced in current consumption of an internal circuit, so that an operation of the internal circuit is stabilized and the operating speed thereof is improved.

摘要翻译： 提供了一种电源电源电容单元，包括连接在副电源线和副地线之间的第一电容器，连接在主电源线和副地线之间的第二电容器和连接在主电源线和副地线之间的第三电容器 在副电源线和主接地线之间。 因此，可以降低内部电路的电流消耗中的副电源线的电压降，使得内部电路的动作稳定，其运转速度提高。

公开(公告)号：US06885235B2

公开(公告)日：2005-04-26

申请号：US10095080

申请日：2002-03-12

申请人： Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Hiroaki Tanizaki ,  Tsukasa Ooishi

发明人： Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Hiroaki Tanizaki ,  Tsukasa Ooishi

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C29/06 ,  G05F3/04

CPC分类号： G11C5/147

摘要： An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

摘要翻译： 内部电源电位产生电路包括连接到内部电源节点的过充电防止电路。 过充电防止电路包括输出由内部电源电位确定的待确定信号的电路，放大要确定的信号之间的电位差和作为输出到节点的参考电位的差分放大电路作为信号 表示应该绘制电流，并且响应于指示应当绘制电流的信号，从内部电源节点抽出电流的电流绘制电路。 因此，感兴趣的半导体集成电路器件可以提供稳定的内部电源电位。

公开(公告)号：US06466509B1

公开(公告)日：2002-10-15

申请号：US10050131

申请日：2002-01-18

申请人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C11/4087 ,  G11C2207/104

摘要： First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.

摘要翻译： 第一和第二存储体设置有M个存储块，每个存储块具有第一和第二存储区域，M表示偶数个不少于两个，以及（M + 1）个读出放大器频带，其布置在每个存储块的相对侧上，并具有 第一选择线和第二选择线分别用于选择第一和第二存储区，第一选择线连接到第一存储体的奇数读出放大器带和第二存储体的偶数读出放大器带 第二选择线连接到第一存储体的偶数读出放大器带和第二存储体的奇数读出放大器带。

公开(公告)号：US06411560B1

公开(公告)日：2002-06-25

申请号：US09987277

申请日：2001-11-14

申请人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C514

CPC分类号： G11C7/1096 ,  G11C5/146 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4074

摘要： A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.

摘要翻译： 第一电源电压被提供给读出放大器的电源节点。 位线驱动器将由第二电源电压组成的列选择信号输出到GIO线路电路的N沟道MOS晶体管的栅极端子。 当输入/输出数据为[1]时，低于第一电源电压的第三电源电压被提供给全局数据线。 在这种情况下，利用所使用的N沟道MOS晶体管的阈值电压，建立关系：第二电源电压<=第三电源电压+阈值电压。 结果，在由具有不同电压电平的多个电源电压驱动的半导体存储器件中，可以减小泄漏电流。

公开(公告)号：US6055206A

公开(公告)日：2000-04-25

申请号：US274623

申请日：1999-03-23

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi ,  Shigeki Tomishima

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi ,  Shigeki Tomishima

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/08 ,  G11C11/401 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C7/1072

摘要： In a synchronous semiconductor memory device of the present invention, a main word driver and a sub decode driver have a function to take in a row decode signal in response to activation of a bank and to maintain the state of the row decode signal. Accordingly, of the circuits associated with row selection, a row pre-decoder, a row decoder and a row system control circuit can operate under a hierarchical power supply structure.

摘要翻译： 在本发明的同步半导体存储器件中，主字驱动器和子解码驱动器具有响应于存储体的激活而获取行解码信号并保持行解码信号的状态的功能。 因此，与行选择相关联的电路中，行预解码器，行解码器和行系统控制电路可以在分层电源结构下操作。

公开(公告)号：US06400632B1

公开(公告)日：2002-06-04

申请号：US09820853

申请日：2001-03-30

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi ,  Shigeki Tomishima ,  Hiroshi Kato

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi ,  Shigeki Tomishima ,  Hiroshi Kato

IPC分类号： G11C700

CPC分类号： G11C17/16 ,  G11C17/18

摘要： The antifuse is brought into an electrically conducted state by setting the voltage Vpgm to a high voltage after activating the signal SA and setting the node N1 once to an L-level. By inversion of the latch, the voltage of the node N1 will be the power source voltage Vcc to bring the transistor into a non-conducted state, whereby the electric current flowing through the antifuse is cut off. A semiconductor device can be provided which includes an antifuse program circuit capable of cutting the electric current off after blowing, so as to prevent decrease in the blowing voltage.

摘要翻译： 通过在激活信号SA之后将电压Vpgm设置为高电压并将节点N1设置为L电平，将反熔丝导入导电状态。 通过锁存器的反相，节点N1的电压将是电源电压Vcc，以使晶体管进入非导通状态，从而切断流过反熔丝的电流。 可以提供一种半导体器件，其包括能够在吹制之后切断电流的反熔丝程序电路，以防止吹送电压的降低。

公开(公告)号：US07233537B2

公开(公告)日：2007-06-19

申请号：US10260397

申请日：2002-10-01

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Takaharu Tsuji ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Takaharu Tsuji ,  Tsukasa Ooishi

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4099 ,  G11C2207/2281

摘要： Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.

摘要翻译： 正常存储单元和虚设单元连续地布置在存储器阵列中。 在数据读取操作中，第一和第二数据线分别连接到所选择的存储单元和虚拟单元，并且被提供有差分放大器的工作电流。 在第一和第二数据线的通过电流之间提供对应于从电压产生电路施加的第一和第二偏移控制电压之间的电压差的偏移，并且通过虚设单元的参考电流被设置为两种之间的水平 的电平对应于通过所选存储单元的数据读取电流的存储数据。

公开(公告)号：US06868029B2

公开(公告)日：2005-03-15

申请号：US10607259

申请日：2003-06-27

申请人： Tsukasa Ooishi ,  Takaharu Tsuji ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Hiroshi Kato

发明人： Tsukasa Ooishi ,  Takaharu Tsuji ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Hiroshi Kato

IPC分类号： G11C11/403 ,  G06F1/26 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  H01L27/148 ,  H03K19/00 ,  H03K19/096

CPC分类号： G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067

摘要： A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

摘要翻译： 逻辑部分向DRAM部分输出指示存储区域的起始地址和结束地址，其中存储的数据在转换到具有降低的电流消耗的掉电模式之前存在。 在断电模式中，刷新控制单元保存起始地址和结束地址，并且仅在需要刷新的区域中控制要进行数据刷新。 逻辑部分的电源在掉电模式下被设置为断开状态，因此半导体器件可以在保持数据的同时消耗电流。

公开(公告)号：US06597617B2

公开(公告)日：2003-07-22

申请号：US10167437

申请日：2002-06-13

申请人： Tsukasa Ooishi ,  Takaharu Tsuji ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Hiroshi Kato

发明人： Tsukasa Ooishi ,  Takaharu Tsuji ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Hiroshi Kato

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067

摘要： A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

公开(公告)号：US06414894B2

公开(公告)日：2002-07-02

申请号：US09778062

申请日：2001-02-07

申请人： Tsukasa Ooishi ,  Takaharu Tsuji ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Hiroshi Kato

发明人： Tsukasa Ooishi ,  Takaharu Tsuji ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Hiroshi Kato

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067

摘要： A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

摘要翻译： 逻辑部分向DRAM部分输出指示存储区域的起始地址和结束地址，其中存储的数据在转换到具有降低的电流消耗的掉电模式之前存在。 在断电模式中，刷新控制单元保存起始地址和结束地址，并且仅在需要刷新的区域中控制要进行数据刷新。 逻辑部分的电源在掉电模式下被设置为断开状态，因此半导体器件可以在保持数据的同时消耗电流。