利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

321 条记录 (耗时 0.027 秒)

    Semiconductor memory device preventing erroneous writing in write operation and delay in read operation
    2.
    发明授权
    Semiconductor memory device preventing erroneous writing in write operation and delay in read operation 有权
    半导体存储器件防止写操作中的错误写入和读操作延迟

    公开(公告)号：US06584005B1

    公开(公告)日：2003-06-24

    申请号：US10302963

    申请日：2002-11-25

    申请人： Hiroshi Kato ,  Masatoshi Ishikawa ,  Tsukasa Ooishi ,  Jun Ohtani ,  Hideto Hidaka

    发明人： Hiroshi Kato ,  Masatoshi Ishikawa ,  Tsukasa Ooishi ,  Jun Ohtani ,  Hideto Hidaka

    IPC分类号： G11C506

    CPC分类号： G11C16/24 ,  G11C7/12 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08

    摘要： In write operation and read operation, a plurality of bit lines are divided into first and second bit line groups based on a selected memory cell column in a memory array. The first bit line group is connected to one of first and second voltages and the second bit line group is connected to the other voltage. Accordingly, when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated in response to activation of the word line. This prevents erroneous writing to the non-selected memory cells and delay in read operation caused by generation of the charging/discharging current.

    摘要翻译： 在写入操作和读取操作中，基于存储器阵列中的所选存储单元列，将多个位线分成第一位线组和第二位线组。 第一位线组连接到第一和第二电压中的一个，并且第二位线组连接到另一个电压。 因此，当对应于所选择的存储单元的字线被激活时，所选存储单元行中未选择的存储单元的源极和漏极被设置为相同的电压电平。 因此，响应于字线的激活，不产生由每个位线的充电和放电产生的充电/放电电流。 这防止了对未选择的存储单元的错误写入和由于产生充电/放电电流引起的读取操作的延迟。

    Thin film magnetic memory device sharing an access element by a plurality of memory cells
    6.
    发明授权
    Thin film magnetic memory device sharing an access element by a plurality of memory cells 失效
    薄膜磁存储器件通过多个存储单元共享存取元件

    公开(公告)号：US06757191B2

    公开(公告)日：2004-06-29

    申请号：US10222793

    申请日：2002-08-19

    申请人： Tsukasa Ooishi ,  Hideto Hidaka ,  Masatoshi Ishikawa

    发明人： Tsukasa Ooishi ,  Hideto Hidaka ,  Masatoshi Ishikawa

    IPC分类号： G11C1114

    CPC分类号： G11C11/16

    摘要： A tunneling magneto-resistance element of each MTJ (magnetic tunnel junction) memory cell is connected between a bit line and a strap. Each strap is shared by a plurality of tunneling magneto-resistance elements that are located adjacent to each other in the row direction in the same sub array. Each access transistor is connected between a corresponding strap and a ground voltage, and turned ON/OFF in response to a corresponding word line. Since data read operation can be conducted with the structure that does not have an access transistor for every tunneling magneto-resistance element, the array area can be reduced.

    摘要翻译： 每个MTJ（磁性隧道结）存储单元的隧道磁阻元件连接在位线和带之间。 每个带由多个相同子阵列中的行方向上彼此相邻的隧道磁阻元件共享。 每个存取晶体管连接在对应的带和接地电压之间，并响应于相应的字线而导通/截止。 由于可以对每个隧道磁阻元件不具有存取晶体管的结构进行数据读取操作，因此可以减小阵列面积。