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1.发明申请公开(公告)号：US20060047986A1
公开(公告)日：2006-03-02
申请号：US10931565
申请日：2004-08-31
申请人： Tsvika Kurts , Alon Naveh , Efraim Rotem , Brad Dendinger , Jorge Rodriguez , Ernest Knoll , David Poisner
发明人： Tsvika Kurts , Alon Naveh , Efraim Rotem , Brad Dendinger , Jorge Rodriguez , Ernest Knoll , David Poisner
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An integrated circuit device, such as a processor initiates a transition to a first power management state. The device then receives a request to exit the first power management state and, in response exits the first power management state at the highest of a reference operating voltage, such as a minimum operating voltage, and a current voltage. For one aspect, an analog to digital converter may be used to determine the current voltage level. Further, for one aspect the first power management state may be a deeper sleep (C4) state, and the processor may quickly exit to a C2 state in response to a bus event such as a bus snoop.
摘要翻译： 诸如处理器的集成电路器件启动向第一电源管理状态的转变。 然后，设备接收到退出第一电源管理状态的请求，并且响应于退出基准工作电压（例如最小工作电压）和当前电压的最高处的第一电源管理状态。 一方面，可以使用模数转换器来确定当前的电压电平。 此外，对于一个方面，第一功率管理状态可以是更深的睡眠（C4）状态，并且处理器可以响应于总线事件（例如总线监听）而快速退出到C2状态。
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2.发明授权公开(公告)号：US07363523B2
公开(公告)日：2008-04-22
申请号：US10931565
申请日：2004-08-31
申请人： Tsvika Kurts , Alon Naveh , Efraim Rotem , Brad M. Dendinger , Jorge P. Rodriguez , Ernest Knoll , David I. Poisner
发明人： Tsvika Kurts , Alon Naveh , Efraim Rotem , Brad M. Dendinger , Jorge P. Rodriguez , Ernest Knoll , David I. Poisner
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An integrated circuit device, such as a processor initiates a transition to a first power management state. The device then receives a request to exit the first power management state and, in response exits the first power management state at the highest of a reference operating voltage, such as a minimum operating voltage, and a current voltage. For one aspect, an analog to digital converter may be used to determine the current voltage level. Further, for one aspect the first power management state may be a deeper sleep (C4) state, and the processor may quickly exit to a C2 state in response to a bus event such as a bus snoop.
摘要翻译： 诸如处理器的集成电路器件启动向第一电源管理状态的转变。 然后，设备接收到退出第一电源管理状态的请求，并且响应于退出基准工作电压（例如最小工作电压）和当前电压的最高处的第一电源管理状态。 一方面，可以使用模数转换器来确定当前的电压电平。 此外，对于一个方面，第一电源管理状态可以是更深的睡眠（C 4）状态，并且处理器可以响应于总线事件（例如总线监听）而快速退出到C 2状态。
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公开(公告)号：US07605668B2
公开(公告)日：2009-10-20
申请号：US11609819
申请日：2006-12-12
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： H03B5/24
CPC分类号： H03B5/20 , H03K3/0315 , H03K5/133 , H03K2005/00045 , H03K2005/00071 , H03L7/0995
摘要： Disclosed herein are embodiments of controllably variable capacitor loads that may be used with delay stages or other elements, for example, in a voltage controlled oscillator.
摘要翻译： 这里公开的可控可变电容器负载的实施例可以与延迟级或其他元件一起使用，例如在压控振荡器中。
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公开(公告)号：US07265637B2
公开(公告)日：2007-09-04
申请号：US11476690
申请日：2006-06-29
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
摘要翻译： 用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。 如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。 这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。 电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。 如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。 在两种操作模式下控制锁相环的方法可以使用上述装置。
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公开(公告)号：US20060244542A1
公开(公告)日：2006-11-02
申请号：US11476690
申请日：2006-06-29
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
摘要翻译： 用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。 如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。 这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。 电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。 如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。 在两种操作模式下控制锁相环的方法可以使用上述装置。
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公开(公告)号：US07120839B2
公开(公告)日：2006-10-10
申请号：US10645660
申请日：2003-08-22
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
CPC分类号： G06F1/04 , H03K5/1565
摘要： A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit includes a self-biased loop that corrects duty-cycle distortions to preferably less than +/−1%. The duty-cycle correction circuit also compensates for changes in a supply voltage. These corrections may take place on a continuous basis, not only during a testing period but also during normal operation of the host system driven by the clock signals.
摘要翻译： 控制电路在宽动态范围内精确地和快速连续的响应来校正时钟信号的占空比失真。 在一个实施例中，占空比校正电路包括将占空比失真校正至优选小于+/- 1％的自偏置环路。 占空比校正电路还补偿电源电压的变化。 不仅在测试期间，而且在由时钟信号驱动的主机系统的正常操作期间，这些校正可以连续进行。
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公开(公告)号：US06546059B1
公开(公告)日：2003-04-08
申请号：US09473585
申请日：1999-12-28
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
IPC分类号： H04L2549
CPC分类号： H03L7/0893 , H03L7/093
摘要： A loop filter in the phase-locked loop includes a capacitor having a specific capacitance value. The loop filter also includes an amplifier coupled to a node of the capacitor. The amplifier amplifies a signal at the node in a way that increases the equivalent capacitance value without physically changing the capacitor.
摘要翻译： 锁相环中的环路滤波器包括具有特定电容值的电容器。 环路滤波器还包括耦合到电容器的节点的放大器。 放大器以增加等效电容值的方式放大节点处的信号，而不会物理改变电容器。
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公开(公告)号：US5357204A
公开(公告)日：1994-10-18
申请号：US115233
申请日：1993-09-01
申请人： Ernest Knoll
发明人： Ernest Knoll
CPC分类号： H03K3/033
摘要： A circuit for generating two internal clocking signals with non-overlapping phases at the frequency of an input external clock. A differentiator means receives a first digital signal and outputs a first digital pulse coupled to a first input of a flip-flop means, causing the flip-flop means to enter a first logic state. A first output of the flip-flop means is provided to an inverter means, which outputs a first internal clocking signal. A second output of the flip-flop means is provided to a second inverter means, which outputs a second internal clocking signal. A reset means is coupled to receive the second output of the flip-flop means and the output of the differentiator means. The reset means provides an output coupled to a second input of the flip-flop means, the reset means provides a second digital pulse in response to a transition in logic state of the second output of the flip-flop means when the flip-flop means enter the first logic state, thereby causing the flip-flop means to enter a second logic state.
摘要翻译： 用于在输入外部时钟的频率处产生具有非重叠相位的两个内部时钟信号的电路。 微分器装置接收第一数字信号并输出耦合到触发器装置的第一输入的第一数字脉冲，使得触发器装置进入第一逻辑状态。 触发器装置的第一输出被提供给反相器装置，其输出第一内部时钟信号。 触发器装置的第二输出被提供给输出第二内部时钟信号的第二反相器装置。 复位装置被耦合以接收触发器装置的第二输出和微分器装置的输出。 复位装置提供耦合到触发器装置的第二输入端的输出，当触发器装置的复位装置响应于触发器装置的第二输出的逻辑状态转变时，复位装置提供第二数字脉冲 进入第一逻辑状态，从而使触发器装置进入第二逻辑状态。
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公开(公告)号：US06922047B2
公开(公告)日：2005-07-26
申请号：US10446838
申请日：2003-05-29
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
摘要翻译： 用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。 如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。 这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。 电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。 如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。 在两种操作模式下控制锁相环的方法可以使用上述装置。
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公开(公告)号：US20050044455A1
公开(公告)日：2005-02-24
申请号：US10645660
申请日：2003-08-22
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
CPC分类号： G06F1/04 , H03K5/1565
摘要： A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit includes a self-biased loop that corrects duty-cycle distortions to preferably less than ±1%. The duty-cycle correction circuit also compensates for changes in a supply voltage. These corrections may take place on a continuous basis, not only during a testing period but also during normal operation of the host system driven by the clock signals.
摘要翻译： 控制电路在宽动态范围内精确地和快速连续的响应来校正时钟信号的占空比失真。 在一个实施例中，占空比校正电路包括将占空比失真校正至优选小于±1％的自偏置环路。 占空比校正电路还补偿电源电压的变化。 不仅在测试期间，而且在由时钟信号驱动的主机系统的正常操作期间，这些校正可以连续进行。
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