公开(公告)号：US08598028B2

公开(公告)日：2013-12-03

申请号：US13335771

申请日：2011-12-22

Applicant: Che-Hao Tu ,  Chi-Jen Liu ,  Tzu-Chung Wang ,  Weilun Hong ,  Ying-Tsung Chen ,  Liang-Guang Chen

Inventor： Che-Hao Tu ,  Chi-Jen Liu ,  Tzu-Chung Wang ,  Weilun Hong ,  Ying-Tsung Chen ,  Liang-Guang Chen

IPC: H01L21/3205 ,  H01L21/20

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/31053 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底的iso区域上形成第一栅极结构，并且在衬底的致密区域上形成第二栅极结构。 密集区域具有比iso区域更大的图案密度。 第一和第二栅极结构各自具有设置在其上的相应的硬掩模。 该方法包括从第一和第二栅极结构去除硬掩模。 从第二栅极结构去除硬掩模导致在第二栅极结构中形成开口。 该方法包括执行沉积过程，随后进行第一抛光工艺以在开口中形成牺牲部件。 该方法包括执行第二抛光工艺以去除牺牲部件以及第一和第二栅极结构的部分。

公开(公告)号：USD504708S1

公开(公告)日：2005-05-03

申请号：US29212898

申请日：2004-09-08

Applicant: Tzu-Chung Wang

Designer： Tzu-Chung Wang

公开(公告)号：US09595477B2

公开(公告)日：2017-03-14

申请号：US13010028

申请日：2011-01-20

Applicant: Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

Inventor： Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

IPC: H01L21/4763 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

Abstract translation: 描述了一种方法，其包括提供衬底并形成邻接衬底上的栅极结构的第一间隔物材料层。 第二间隔材料层邻近并邻接栅极结构并且覆盖第一间隔物层形成。 然后分别同时蚀刻第一间隔材料层和第二间隔材料层以形成第一和第二间隔物。 在衬底上形成（例如，生长）外延区域，其包括与第一和第二间隔物中的每一个的界面。 随后可以移除第二间隔物，并且保留在器件上的第一间隔物减小ILD间隙填充的纵横比。 第一间隔物的实例组成是SiCN。

公开(公告)号：US20120187459A1

公开(公告)日：2012-07-26

申请号：US13010028

申请日：2011-01-20

Applicant: Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

Inventor： Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

IPC: H01L29/772 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

Abstract translation: 描述了一种方法，其包括提供衬底并形成邻接衬底上的栅极结构的第一间隔物材料层。 第二间隔材料层邻近并邻接栅极结构并且覆盖第一间隔物层形成。 然后分别同时蚀刻第一间隔材料层和第二间隔材料层以形成第一和第二间隔物。 在衬底上形成（例如，生长）外延区域，其包括与第一和第二间隔物中的每一个的界面。 随后可以移除第二间隔物，并且保留在器件上的第一间隔物减小ILD间隙填充的纵横比。 第一间隔物的实例组成是SiCN。

公开(公告)号：USD504052S1

公开(公告)日：2005-04-19

申请号：US29197086

申请日：2004-01-10

Applicant: Tzu-Chung Wang

Designer： Tzu-Chung Wang

公开(公告)号：US20130164930A1

公开(公告)日：2013-06-27

申请号：US13335771

申请日：2011-12-22

Applicant: Che-Hao Tu ,  Chi-Jen Liu ,  Tzu-Chung Wang ,  Weilun Hong ,  Ying-Tsung Chen ,  Liang-Guang Chen

Inventor： Che-Hao Tu ,  Chi-Jen Liu ,  Tzu-Chung Wang ,  Weilun Hong ,  Ying-Tsung Chen ,  Liang-Guang Chen

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/31053 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底的iso区域上形成第一栅极结构，并且在衬底的致密区域上形成第二栅极结构。 密集区域具有比iso区域更大的图案密度。 第一和第二栅极结构各自具有设置在其上的相应的硬掩模。 该方法包括从第一和第二栅极结构去除硬掩模。 从第二栅极结构去除硬掩模导致在第二栅极结构中形成开口。 该方法包括执行沉积过程，随后进行第一抛光工艺以在开口中形成牺牲部件。 该方法包括执行第二抛光工艺以去除牺牲部件以及第一和第二栅极结构的部分。

公开(公告)号：USD482276S1

公开(公告)日：2003-11-18

申请号：US29174277

申请日：2003-01-14

Applicant: Tzu-Chung Wang

Designer： Tzu-Chung Wang