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公开(公告)号：US20240162220A1
公开(公告)日：2024-05-16
申请号：US18078064
申请日：2022-12-08
发明人： Hsin-Yu Chen , Chun-Hao Lin , Yuan-Ting Chuang , Shou-Wei Hsieh
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629 , H01L21/823475 , H01L28/75 , H01L28/87 , H01L28/91
摘要： A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.
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公开(公告)号：US20210210628A1
公开(公告)日：2021-07-08
申请号：US17207751
申请日：2021-03-22
发明人： Cheng-Han Wu , Hsin-Yu Chen , Chun-Hao Lin , Shou-Wei Hsieh , Chih-Ming Su , Yi-Ren Chen , Yuan-Ting Chuang
IPC分类号： H01L29/78 , H01L21/762 , H01L29/417
摘要： A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.
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公开(公告)号：US20190096771A1
公开(公告)日：2019-03-28
申请号：US15786608
申请日：2017-10-18
发明人： Chun-Hao Lin , Hsin-Yu Chen , Shou-Wei Hsieh
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/161
摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.
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公开(公告)号：US20190043964A1
公开(公告)日：2019-02-07
申请号：US15690260
申请日：2017-08-29
发明人： Chun-Hao Lin , Hsin-Yu Chen , Shou-Wei Hsieh
IPC分类号： H01L29/66 , H01L21/762 , H01L21/3105 , H01L29/06
摘要： A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; removing the second gate structure and part of the fin-shaped structure to forma first trench; forming a dielectric layer into the first trench; and planarizing part of the dielectric layer to form a single diffusion break (SDB) structure. Preferably, the top surfaces of the SDB structure and the first gate structure are coplanar.
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公开(公告)号：US20190043858A1
公开(公告)日：2019-02-07
申请号：US15691703
申请日：2017-08-30
发明人： Chun-Hao Lin , Hsin-Yu Chen , Shou-Wei Hsieh
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/308 , H01L21/311 , H01L29/66 , H01L21/762 , H01L29/06 , H01L27/02
摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.
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公开(公告)号：US20170069543A1
公开(公告)日：2017-03-09
申请号：US14884746
申请日：2015-10-15
发明人： Ching-Yu Chang , Li-Wei Feng , Shih-Hung Tsai , Ssu-I Fu , Jyh-Shyang Jenq , Chien-Ting Lin , Yi-Ren Chen , Shou-Wei Hsieh , Hsin-Yu Chen , Chun-Hao Lin
IPC分类号： H01L21/8238 , H01L21/324
CPC分类号： H01L21/823821 , H01L21/02129 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823878
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.
摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的衬底和围绕鳍状结构的浅沟槽隔离（STI），其中鳍状结构具有顶部和底部; 在STI和顶部上形成第一掺杂层; 并执行第一退火处理。
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公开(公告)号：US11876095B2
公开(公告)日：2024-01-16
申请号：US17367447
申请日：2021-07-05
发明人： Chun-Hao Lin , Hsin-Yu Chen , Shou-Wei Hsieh
IPC分类号： H01L27/08 , H01L27/088 , H01L21/8234 , H01L21/308 , H01L21/311 , H01L27/02 , H01L21/762 , H01L29/06 , H01L29/66 , H01L21/84
CPC分类号： H01L27/0886 , H01L21/308 , H01L21/31144 , H01L21/76224 , H01L21/823412 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823481 , H01L27/0207 , H01L29/0649 , H01L29/0657 , H01L29/66545 , H01L29/66818 , H01L21/845
摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.
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公开(公告)号：US11581422B2
公开(公告)日：2023-02-14
申请号：US17161707
申请日：2021-01-29
发明人： Chun-Hao Lin , Hsin-Yu Chen , Shou-Wei Hsieh
IPC分类号： H01L29/66 , H01L21/762
摘要： A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.
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公开(公告)号：US20210159322A1
公开(公告)日：2021-05-27
申请号：US17161696
申请日：2021-01-29
发明人： Chun-Hao Lin , Hsin-Yu Chen , Shou-Wei Hsieh
IPC分类号： H01L29/66 , H01L21/762
摘要： A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.
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公开(公告)号：US20200312984A1
公开(公告)日：2020-10-01
申请号：US16396777
申请日：2019-04-29
发明人： Chun-Hao Lin , Hsin-Yu Chen , Shou-Wei Hsieh
IPC分类号： H01L29/66 , H01L21/762
摘要： A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.
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